From dd32ba337aab88c215108ca8bf4a0267fce1e773 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Thu, 11 Aug 2011 22:05:09 +0000 Subject: [PATCH] ARM load shifted register pre-index fix shift value asm parser encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137367 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 +- test/MC/ARM/arm-memory-instructions.s | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 39f873c8beb..07570ae8e20 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -830,7 +830,7 @@ public: // For register offset, we encode the shift type and negation flag // here. Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, - 0, Mem.ShiftType); + Mem.ShiftImm, Mem.ShiftType); } Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum)); diff --git a/test/MC/ARM/arm-memory-instructions.s b/test/MC/ARM/arm-memory-instructions.s index 18fec83c601..783ac28ced9 100644 --- a/test/MC/ARM/arm-memory-instructions.s +++ b/test/MC/ARM/arm-memory-instructions.s @@ -38,6 +38,7 @@ _func: ldr r2, [r5, -r3] ldr r1, [r5, r9]! ldr r6, [r7, -r8]! + ldr r1, [r0, r2, lsr #3]! ldr r5, [r9], r2 ldr r4, [r3], -r6 ldr r3, [r8, -r2, lsl #15] @@ -47,6 +48,7 @@ _func: @ CHECK: ldr r2, [r5, -r3] @ encoding: [0x03,0x20,0x15,0xe7] @ CHECK: ldr r1, [r5, r9]! @ encoding: [0x09,0x10,0xb5,0xe7] @ CHECK: ldr r6, [r7, -r8]! @ encoding: [0x08,0x60,0x37,0xe7] +@ CHECK: ldr r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7] @ CHECK: ldr r5, [r9], r2 @ encoding: [0x02,0x50,0x99,0xe6] @ CHECK: ldr r4, [r3], -r6 @ encoding: [0x06,0x40,0x13,0xe6] @ CHECK: ldr r3, [r8, -r2, lsl #15] @ encoding: [0x82,0x37,0x18,0xe7]