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Rename X86ATTAsmParser -> X86AsmParser

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We are using one parser to parse att as well as intel style syntax.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148032 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Devang Patel
2012-01-12 18:03:40 +00:00
parent b20b518f80
commit dd929fc704
2 changed files with 18 additions and 19 deletions
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34
lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@@ -31,7 +31,7 @@ using namespace llvm;
namespace { namespace {
struct X86Operand; struct X86Operand;
class X86ATTAsmParser : public MCTargetAsmParser { class X86AsmParser : public MCTargetAsmParser {
MCSubtargetInfo &STI; MCSubtargetInfo &STI;
MCAsmParser &Parser; MCAsmParser &Parser;
@@ -83,7 +83,7 @@ private:
/// } /// }
public: public:
X86ATTAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser) X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
: MCTargetAsmParser(), STI(sti), Parser(parser) { : MCTargetAsmParser(), STI(sti), Parser(parser) {
// Initialize the set of available features. // Initialize the set of available features.
@@ -424,7 +424,7 @@ struct X86Operand : public MCParsedAsmOperand {
} // end anonymous namespace. } // end anonymous namespace.
bool X86ATTAsmParser::isSrcOp(X86Operand &Op) { bool X86AsmParser::isSrcOp(X86Operand &Op) {
unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI; unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI;
return (Op.isMem() && return (Op.isMem() &&
@@ -434,7 +434,7 @@ bool X86ATTAsmParser::isSrcOp(X86Operand &Op) {
Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0); Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0);
} }
bool X86ATTAsmParser::isDstOp(X86Operand &Op) { bool X86AsmParser::isDstOp(X86Operand &Op) {
unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI; unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI;
return Op.isMem() && Op.Mem.SegReg == X86::ES && return Op.isMem() && Op.Mem.SegReg == X86::ES &&
@@ -443,8 +443,8 @@ bool X86ATTAsmParser::isDstOp(X86Operand &Op) {
Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0; Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0;
} }
bool X86ATTAsmParser::ParseRegister(unsigned &RegNo, bool X86AsmParser::ParseRegister(unsigned &RegNo,
SMLoc &StartLoc, SMLoc &EndLoc) { SMLoc &StartLoc, SMLoc &EndLoc) {
RegNo = 0; RegNo = 0;
const AsmToken &TokPercent = Parser.getTok(); const AsmToken &TokPercent = Parser.getTok();
assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!"); assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!");
@@ -543,7 +543,7 @@ bool X86ATTAsmParser::ParseRegister(unsigned &RegNo,
return false; return false;
} }
X86Operand *X86ATTAsmParser::ParseOperand() { X86Operand *X86AsmParser::ParseOperand() {
if (getParser().getAssemblerDialect()) if (getParser().getAssemblerDialect())
return ParseIntelOperand(); return ParseIntelOperand();
return ParseATTOperand(); return ParseATTOperand();
@@ -573,7 +573,7 @@ static bool isIntelMemOperand(StringRef OpStr, unsigned &Size) {
return Size != 0; return Size != 0;
} }
X86Operand *X86ATTAsmParser::ParseIntelOperand() { X86Operand *X86AsmParser::ParseIntelOperand() {
const AsmToken &Tok = Parser.getTok(); const AsmToken &Tok = Parser.getTok();
SMLoc Start = Parser.getTok().getLoc(), End; SMLoc Start = Parser.getTok().getLoc(), End;
@@ -636,7 +636,7 @@ X86Operand *X86ATTAsmParser::ParseIntelOperand() {
return 0; return 0;
} }
X86Operand *X86ATTAsmParser::ParseATTOperand() { X86Operand *X86AsmParser::ParseATTOperand() {
switch (getLexer().getKind()) { switch (getLexer().getKind()) {
default: default:
// Parse a memory operand with no segment register. // Parse a memory operand with no segment register.
@@ -675,7 +675,7 @@ X86Operand *X86ATTAsmParser::ParseATTOperand() {
/// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
/// has already been parsed if present. /// has already been parsed if present.
X86Operand *X86ATTAsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) { X86Operand *X86AsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
// We have to disambiguate a parenthesized expression "(4+5)" from the start // We have to disambiguate a parenthesized expression "(4+5)" from the start
// of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
@@ -806,7 +806,7 @@ X86Operand *X86ATTAsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
MemStart, MemEnd); MemStart, MemEnd);
} }
bool X86ATTAsmParser:: bool X86AsmParser::
ParseInstruction(StringRef Name, SMLoc NameLoc, ParseInstruction(StringRef Name, SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands) { SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
StringRef PatchedName = Name; StringRef PatchedName = Name;
@@ -1091,7 +1091,7 @@ ParseInstruction(StringRef Name, SMLoc NameLoc,
return false; return false;
} }
bool X86ATTAsmParser:: bool X86AsmParser::
MatchAndEmitInstruction(SMLoc IDLoc, MatchAndEmitInstruction(SMLoc IDLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands, SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out) { MCStreamer &Out) {
@@ -1273,7 +1273,7 @@ MatchAndEmitInstruction(SMLoc IDLoc,
} }
bool X86ATTAsmParser::ParseDirective(AsmToken DirectiveID) { bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
StringRef IDVal = DirectiveID.getIdentifier(); StringRef IDVal = DirectiveID.getIdentifier();
if (IDVal == ".word") if (IDVal == ".word")
return ParseDirectiveWord(2, DirectiveID.getLoc()); return ParseDirectiveWord(2, DirectiveID.getLoc());
@@ -1284,7 +1284,7 @@ bool X86ATTAsmParser::ParseDirective(AsmToken DirectiveID) {
/// ParseDirectiveWord /// ParseDirectiveWord
/// ::= .word [ expression (, expression)* ] /// ::= .word [ expression (, expression)* ]
bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) { bool X86AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
if (getLexer().isNot(AsmToken::EndOfStatement)) { if (getLexer().isNot(AsmToken::EndOfStatement)) {
for (;;) { for (;;) {
const MCExpr *Value; const MCExpr *Value;
@@ -1309,7 +1309,7 @@ bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
/// ParseDirectiveCode /// ParseDirectiveCode
/// ::= .code32 | .code64 /// ::= .code32 | .code64
bool X86ATTAsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) { bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
if (IDVal == ".code32") { if (IDVal == ".code32") {
Parser.Lex(); Parser.Lex();
if (is64BitMode()) { if (is64BitMode()) {
@@ -1334,8 +1334,8 @@ extern "C" void LLVMInitializeX86AsmLexer();
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializeX86AsmParser() { extern "C" void LLVMInitializeX86AsmParser() {
RegisterMCAsmParser<X86ATTAsmParser> X(TheX86_32Target); RegisterMCAsmParser<X86AsmParser> X(TheX86_32Target);
RegisterMCAsmParser<X86ATTAsmParser> Y(TheX86_64Target); RegisterMCAsmParser<X86AsmParser> Y(TheX86_64Target);
LLVMInitializeX86AsmLexer(); LLVMInitializeX86AsmLexer();
} }

3
lib/Target/X86/X86.td
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@@ -248,9 +248,8 @@ include "X86CallingConv.td"
// Assembly Parser // Assembly Parser
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Currently the X86 assembly parser only supports ATT syntax.
def ATTAsmParser : AsmParser { def ATTAsmParser : AsmParser {
string AsmParserClassName = "ATTAsmParser"; string AsmParserClassName = "AsmParser";
} }
def ATTAsmParserVariant : AsmParserVariant { def ATTAsmParserVariant : AsmParserVariant {