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Latency between CPSR def and branch is zero.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117192 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2010-10-23 02:04:38 +00:00
parent 7871687604
commit dd9dd6f857
1 changed files with 6 additions and 0 deletions
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6
lib/Target/ARM/ARMBaseInstrInfo.cpp
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@ -1892,7 +1892,13 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
if (!ItinData || ItinData->isEmpty())
return DefTID.mayLoad() ? 3 : 1;
const TargetInstrDesc &UseTID = UseMI->getDesc();
const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
if (DefMO.getReg() == ARM::CPSR && UseTID.isBranch())
// CPSR set and branch can be paired in the same cycle.
return 0;
unsigned DefAlign = DefMI->hasOneMemOperand()
? (*DefMI->memoperands_begin())->getAlignment() : 0;
unsigned UseAlign = UseMI->hasOneMemOperand()