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[mips] Make load/store accumulator pseudo instructions codeGenOnly. Also,

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remove lines that are setting DecoderNamespace for pseudo atomic instructions.

No intended functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187632 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2013-08-01 23:14:16 +00:00
parent 186f8f9d41
commit ddbdeefa28
2 changed files with 11 additions and 22 deletions
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18
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -37,21 +37,15 @@ def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
let DecoderNamespace = "Mips64" in {
multiclass Atomic2Ops64<PatFrag Op> {
def NAME : Atomic2Ops<Op, CPU64Regs, CPURegs>,
Requires<[NotN64, HasStdEnc]>;
def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>,
Requires<[IsN64, HasStdEnc]> {
let isCodeGenOnly = 1;
}
def NAME : Atomic2Ops<Op, CPU64Regs, CPURegs>, Requires<[NotN64, HasStdEnc]>;
def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>, Requires<[IsN64, HasStdEnc]>;
}
multiclass AtomicCmpSwap64<PatFrag Op> {
def NAME : AtomicCmpSwap<Op, CPU64Regs, CPURegs>,
Requires<[NotN64, HasStdEnc]>;
def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>,
Requires<[IsN64, HasStdEnc]> {
let isCodeGenOnly = 1;
}
Requires<[IsN64, HasStdEnc]>;
}
}
let usesCustomInserter = 1, Predicates = [HasStdEnc],
@ -67,9 +61,9 @@ let usesCustomInserter = 1, Predicates = [HasStdEnc],
}
/// Pseudo instructions for loading and storing accumulator registers.
let isPseudo = 1 in {
defm LOAD_AC128 : LoadM<"load_ac128", ACRegs128>;
defm STORE_AC128 : StoreM<"store_ac128", ACRegs128>;
let isPseudo = 1, isCodeGenOnly = 1 in {
defm LOAD_AC128 : LoadM<"", ACRegs128>;
defm STORE_AC128 : StoreM<"", ACRegs128>;
}
//===----------------------------------------------------------------------===//

15
lib/Target/Mips/MipsInstrInfo.td
View File

@ -791,10 +791,7 @@ class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
multiclass Atomic2Ops32<PatFrag Op> {
def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>;
def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>,
Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
}
def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, Requires<[IsN64, HasStdEnc]>;
}
// Atomic Compare & Swap.
@ -806,9 +803,7 @@ multiclass AtomicCmpSwap32<PatFrag Op> {
def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>,
Requires<[NotN64, HasStdEnc]>;
def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>,
Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
}
Requires<[IsN64, HasStdEnc]>;
}
class LLBase<string opstr, RegisterOperand RO, Operand Mem> :
@ -879,9 +874,9 @@ let usesCustomInserter = 1 in {
}
/// Pseudo instructions for loading and storing accumulator registers.
let isPseudo = 1 in {
defm LOAD_AC64 : LoadM<"load_ac64", ACRegs>;
defm STORE_AC64 : StoreM<"store_ac64", ACRegs>;
let isPseudo = 1, isCodeGenOnly = 1 in {
defm LOAD_AC64 : LoadM<"", ACRegs>;
defm STORE_AC64 : StoreM<"", ACRegs>;
}
//===----------------------------------------------------------------------===//