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Add support for 128 bit shifts and 32 bit shifts

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on 16 bit machines.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53458 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duncan Sands 2008-07-11 16:52:29 +00:00
parent 7d9843fc37
commit dddc6291fb
3 changed files with 26 additions and 6 deletions
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3
include/llvm/CodeGen/RuntimeLibcalls.h
View File

@ -29,10 +29,13 @@ namespace RTLIB {
// Integer
SHL_I32,
SHL_I64,
SHL_I128,
SRL_I32,
SRL_I64,
SRL_I128,
SRA_I32,
SRA_I64,
SRA_I128,
MUL_I32,
MUL_I64,
MUL_I128,

26
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -1454,21 +1454,35 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
}
// Otherwise, emit a libcall.
assert(VT == MVT::i64 && "Unsupported shift!");
RTLIB::Libcall LC;
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
bool isSigned;
if (N->getOpcode() == ISD::SHL) {
LC = RTLIB::SHL_I64;
isSigned = false; /*sign irrelevant*/
if (VT == MVT::i32)
LC = RTLIB::SHL_I32;
else if (VT == MVT::i64)
LC = RTLIB::SHL_I64;
else if (VT == MVT::i128)
LC = RTLIB::SHL_I128;
} else if (N->getOpcode() == ISD::SRL) {
LC = RTLIB::SRL_I64;
isSigned = false;
if (VT == MVT::i32)
LC = RTLIB::SRL_I32;
else if (VT == MVT::i64)
LC = RTLIB::SRL_I64;
else if (VT == MVT::i128)
LC = RTLIB::SRL_I128;
} else {
assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
LC = RTLIB::SRA_I64;
isSigned = true;
if (VT == MVT::i32)
LC = RTLIB::SRA_I32;
else if (VT == MVT::i64)
LC = RTLIB::SRA_I64;
else if (VT == MVT::i128)
LC = RTLIB::SRA_I128;
}
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!");
SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi);

3
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -31,10 +31,13 @@ using namespace llvm;
static void InitLibcallNames(const char **Names) {
Names[RTLIB::SHL_I32] = "__ashlsi3";
Names[RTLIB::SHL_I64] = "__ashldi3";
Names[RTLIB::SHL_I128] = "__ashlti3";
Names[RTLIB::SRL_I32] = "__lshrsi3";
Names[RTLIB::SRL_I64] = "__lshrdi3";
Names[RTLIB::SRL_I128] = "__lshrti3";
Names[RTLIB::SRA_I32] = "__ashrsi3";
Names[RTLIB::SRA_I64] = "__ashrdi3";
Names[RTLIB::SRA_I128] = "__ashrti3";
Names[RTLIB::MUL_I32] = "__mulsi3";
Names[RTLIB::MUL_I64] = "__muldi3";
Names[RTLIB::MUL_I128] = "__multi3";