diff --git a/lib/Target/AArch64/AArch64InstrNEON.td b/lib/Target/AArch64/AArch64InstrNEON.td index a273468041c..04167a14bb8 100644 --- a/lib/Target/AArch64/AArch64InstrNEON.td +++ b/lib/Target/AArch64/AArch64InstrNEON.td @@ -1437,9 +1437,8 @@ let isReMaterializable = 1 in { def MOVIdi : NeonI_1VModImm<0b0, 0b1, (outs FPR64:$Rd), (ins neon_uimm64_mask:$Imm), "movi\t $Rd, $Imm", - [(set (f64 FPR64:$Rd), - (f64 (bitconvert - (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))))], + [(set (v1i64 FPR64:$Rd), + (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))], NoItinerary> { let cmode = 0b1110; } diff --git a/test/CodeGen/AArch64/neon-aba-abd.ll b/test/CodeGen/AArch64/neon-aba-abd.ll index ee22a45c751..54009849ef6 100644 --- a/test/CodeGen/AArch64/neon-aba-abd.ll +++ b/test/CodeGen/AArch64/neon-aba-abd.ll @@ -157,6 +157,16 @@ define <2 x i32> @test_sabd_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { ret <2 x i32> %abd } +define <2 x i32> @test_sabd_v2i32_const() { +; CHECK: test_sabd_v2i32_const: +; CHECK: movi d1, #0xffffffff0000 +; CHECK-NEXT: sabd v0.2s, v0.2s, v1.2s + %1 = tail call <2 x i32> @llvm.arm.neon.vabds.v2i32( + <2 x i32> , + <2 x i32> ) + ret <2 x i32> %1 +} + define <2 x i32> @test_saba_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { ; CHECK: test_saba_v2i32: %abd = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) diff --git a/test/CodeGen/AArch64/neon-mov.ll b/test/CodeGen/AArch64/neon-mov.ll index 42f6a894da6..60b13b8b9a0 100644 --- a/test/CodeGen/AArch64/neon-mov.ll +++ b/test/CodeGen/AArch64/neon-mov.ll @@ -202,4 +202,16 @@ define <2 x double> @fmov2d() { ret <2 x double> < double -1.2e1, double -1.2e1> } +define <2 x i32> @movi1d_1() { +; CHECK: movi d0, #0xffffffff0000 + ret <2 x i32> < i32 -65536, i32 65535> +} + + +declare <2 x i32> @test_movi1d(<2 x i32>, <2 x i32>) +define <2 x i32> @movi1d() { +; CHECK: movi d1, #0xffffffff0000 + %1 = tail call <2 x i32> @test_movi1d(<2 x i32> , <2 x i32> ) + ret <2 x i32> %1 +}