From ddfbd5805478cf108156bb0159b7495d2b236f7e Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Wed, 11 Sep 2013 10:15:48 +0000 Subject: [PATCH] [mips][msa] Separate the configuration of int/float vector types since they will diverge soon No functional change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190506 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsSEISelLowering.cpp | 30 +++++++++++++++++++------- lib/Target/Mips/MipsSEISelLowering.h | 4 +++- 2 files changed, 25 insertions(+), 9 deletions(-) diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp index 2436e540f14..5999e197f36 100644 --- a/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/lib/Target/Mips/MipsSEISelLowering.cpp @@ -83,13 +83,13 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) setOperationAction(ISD::MUL, MVT::v2i16, Legal); if (Subtarget->hasMSA()) { - addMSAType(MVT::v16i8, &Mips::MSA128BRegClass); - addMSAType(MVT::v8i16, &Mips::MSA128HRegClass); - addMSAType(MVT::v4i32, &Mips::MSA128WRegClass); - addMSAType(MVT::v2i64, &Mips::MSA128DRegClass); - addMSAType(MVT::v8f16, &Mips::MSA128HRegClass); - addMSAType(MVT::v4f32, &Mips::MSA128WRegClass); - addMSAType(MVT::v2f64, &Mips::MSA128DRegClass); + addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass); + addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass); + addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass); + addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass); + addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass); + addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass); + addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass); } if (!Subtarget->mipsSEUsesSoftFloat()) { @@ -148,7 +148,21 @@ llvm::createMipsSETargetLowering(MipsTargetMachine &TM) { } void MipsSETargetLowering:: -addMSAType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { +addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { + addRegisterClass(Ty, RC); + + // Expand all builtin opcodes. + for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) + setOperationAction(Opc, Ty, Expand); + + setOperationAction(ISD::BITCAST, Ty, Legal); + setOperationAction(ISD::LOAD, Ty, Legal); + setOperationAction(ISD::STORE, Ty, Legal); + +} + +void MipsSETargetLowering:: +addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { addRegisterClass(Ty, RC); // Expand all builtin opcodes. diff --git a/lib/Target/Mips/MipsSEISelLowering.h b/lib/Target/Mips/MipsSEISelLowering.h index dde0c23c35d..016d4adbf73 100644 --- a/lib/Target/Mips/MipsSEISelLowering.h +++ b/lib/Target/Mips/MipsSEISelLowering.h @@ -22,7 +22,9 @@ namespace llvm { public: explicit MipsSETargetLowering(MipsTargetMachine &TM); - void addMSAType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC); + void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC); + void addMSAFloatType(MVT::SimpleValueType Ty, + const TargetRegisterClass *RC); virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;