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[SystemZ] Use ROSBG and non-zero form of RISBG for OR nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186405 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford
parent
ab42fc66b1
commit
de25544a73
@ -222,6 +222,11 @@ class SystemZDAGToDAGISel : public SelectionDAGISel {
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Addr, Base, Disp, Index);
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}
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// Check whether (or Op (and X InsertMask)) is effectively an insertion
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// of X into bits InsertMask of some Y != Op. Return true if so and
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// set Op to that Y.
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bool detectOrAndInsertion(SDValue &Op, uint64_t InsertMask);
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// Try to fold some of Ops.Input into other fields of Ops. Return true
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// on success.
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bool expandRISBG(RISBGOperands &Ops);
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@ -236,6 +241,10 @@ class SystemZDAGToDAGISel : public SelectionDAGISel {
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// Return the selected node on success, otherwise return null.
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SDNode *tryRISBGZero(SDNode *N);
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// Try to use RISBG or ROSBG to implement OR node N. Return the selected
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// node on success, otherwise return null.
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SDNode *tryRISBGOrROSBG(SDNode *N);
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// If Op0 is null, then Node is a constant that can be loaded using:
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//
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// (Opcode UpperVal LowerVal)
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@ -557,6 +566,38 @@ bool SystemZDAGToDAGISel::selectBDXAddr(SystemZAddressingMode::AddrForm Form,
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return true;
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}
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bool SystemZDAGToDAGISel::detectOrAndInsertion(SDValue &Op,
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uint64_t InsertMask) {
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// We're only interested in cases where the insertion is into some operand
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// of Op, rather than into Op itself. The only useful case is an AND.
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if (Op.getOpcode() != ISD::AND)
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return false;
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// We need a constant mask.
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ConstantSDNode *MaskNode =
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dyn_cast<ConstantSDNode>(Op.getOperand(1).getNode());
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if (!MaskNode)
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return false;
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// It's not an insertion of Op.getOperand(0) if the two masks overlap.
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uint64_t AndMask = MaskNode->getZExtValue();
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if (InsertMask & AndMask)
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return false;
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// It's only an insertion if all bits are covered or are known to be zero.
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// The inner check covers all cases but is more expensive.
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uint64_t Used = allOnes(Op.getValueType().getSizeInBits());
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if (Used != (AndMask | InsertMask)) {
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APInt KnownZero, KnownOne;
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CurDAG->ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne);
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if (Used != (AndMask | InsertMask | KnownZero.getZExtValue()))
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return false;
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}
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Op = Op.getOperand(0);
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return true;
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}
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// Return true if Mask matches the regexp 0*1+0*, given that zero masks
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// have already been filtered out. Store the first set bit in LSB and
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// the number of set bits in Length if so.
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@ -761,6 +802,47 @@ SDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {
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return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode();
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}
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SDNode *SystemZDAGToDAGISel::tryRISBGOrROSBG(SDNode *N) {
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// Try treating each operand of N as the second operand of RISBG or ROSBG
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// and see which goes deepest.
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RISBGOperands RISBG[] = { N->getOperand(0), N->getOperand(1) };
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unsigned Count[] = { 0, 0 };
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for (unsigned I = 0; I < 2; ++I)
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while (expandRISBG(RISBG[I]))
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Count[I] += 1;
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// Do nothing if neither operand is suitable.
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if (Count[0] == 0 && Count[1] == 0)
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return 0;
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// Pick the deepest second operand.
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unsigned I = Count[0] > Count[1] ? 0 : 1;
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SDValue Op0 = N->getOperand(I ^ 1);
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// Prefer IC for character insertions from memory.
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if ((RISBG[I].Mask & 0xff) == 0)
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if (LoadSDNode *Load = dyn_cast<LoadSDNode>(Op0.getNode()))
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if (Load->getMemoryVT() == MVT::i8)
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return 0;
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// See whether we can avoid an AND in the first operand by converting
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// ROSBG to RISBG.
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unsigned Opcode = SystemZ::ROSBG;
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if (detectOrAndInsertion(Op0, RISBG[I].Mask))
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Opcode = SystemZ::RISBG;
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EVT VT = N->getValueType(0);
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SDValue Ops[5] = {
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convertTo(SDLoc(N), MVT::i64, Op0),
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convertTo(SDLoc(N), MVT::i64, RISBG[I].Input),
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CurDAG->getTargetConstant(RISBG[I].Start, MVT::i32),
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CurDAG->getTargetConstant(RISBG[I].End, MVT::i32),
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CurDAG->getTargetConstant(RISBG[I].Rotate, MVT::i32)
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};
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N = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i64, Ops);
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return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode();
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}
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SDNode *SystemZDAGToDAGISel::splitLargeImmediate(unsigned Opcode, SDNode *Node,
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SDValue Op0, uint64_t UpperVal,
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uint64_t LowerVal) {
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@ -833,10 +915,13 @@ SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
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SDNode *ResNode = 0;
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switch (Opcode) {
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case ISD::OR:
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if (Node->getOperand(1).getOpcode() != ISD::Constant)
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ResNode = tryRISBGOrROSBG(Node);
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// Fall through.
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case ISD::XOR:
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// If this is a 64-bit operation in which both 32-bit halves are nonzero,
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// split the operation into two.
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if (Node->getValueType(0) == MVT::i64)
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if (!ResNode && Node->getValueType(0) == MVT::i64)
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if (ConstantSDNode *Op1 = dyn_cast<ConstantSDNode>(Node->getOperand(1))) {
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uint64_t Val = Op1->getZExtValue();
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if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val))
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93
test/CodeGen/SystemZ/risbg-02.ll
Normal file
93
test/CodeGen/SystemZ/risbg-02.ll
Normal file
@ -0,0 +1,93 @@
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; Test sequences that can use RISBG with a normal first operand.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test a case with two ANDs.
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define i32 @f1(i32 %a, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: risbg %r2, %r3, 60, 62, 0
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; CHECK: br %r14
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%anda = and i32 %a, -15
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%andb = and i32 %b, 14
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%or = or i32 %anda, %andb
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ret i32 %or
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}
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; ...and again with i64.
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define i64 @f2(i64 %a, i64 %b) {
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; CHECK-LABEL: f2:
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; CHECK: risbg %r2, %r3, 60, 62, 0
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; CHECK: br %r14
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%anda = and i64 %a, -15
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%andb = and i64 %b, 14
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%or = or i64 %anda, %andb
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ret i64 %or
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}
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; Test a case with two ANDs and a shift.
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define i32 @f3(i32 %a, i32 %b) {
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; CHECK-LABEL: f3:
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; CHECK: risbg %r2, %r3, 60, 63, 56
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; CHECK: br %r14
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%anda = and i32 %a, -16
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%shr = lshr i32 %b, 8
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%andb = and i32 %shr, 15
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%or = or i32 %anda, %andb
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ret i32 %or
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}
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; ...and again with i64.
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define i64 @f4(i64 %a, i64 %b) {
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; CHECK-LABEL: f4:
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; CHECK: risbg %r2, %r3, 60, 63, 56
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; CHECK: br %r14
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%anda = and i64 %a, -16
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%shr = lshr i64 %b, 8
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%andb = and i64 %shr, 15
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%or = or i64 %anda, %andb
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ret i64 %or
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}
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; Test a case with a single AND and a left shift.
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define i32 @f5(i32 %a, i32 %b) {
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; CHECK-LABEL: f5:
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; CHECK: risbg %r2, %r3, 32, 53, 10
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; CHECK: br %r14
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%anda = and i32 %a, 1023
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%shlb = shl i32 %b, 10
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%or = or i32 %anda, %shlb
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ret i32 %or
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}
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; ...and again with i64.
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define i64 @f6(i64 %a, i64 %b) {
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; CHECK-LABEL: f6:
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; CHECK: risbg %r2, %r3, 0, 53, 10
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; CHECK: br %r14
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%anda = and i64 %a, 1023
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%shlb = shl i64 %b, 10
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%or = or i64 %anda, %shlb
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ret i64 %or
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}
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; Test a case with a single AND and a right shift.
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define i32 @f7(i32 %a, i32 %b) {
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; CHECK-LABEL: f7:
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; CHECK: risbg %r2, %r3, 40, 63, 56
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; CHECK: br %r14
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%anda = and i32 %a, -16777216
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%shrb = lshr i32 %b, 8
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%or = or i32 %anda, %shrb
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ret i32 %or
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}
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; ...and again with i64.
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define i64 @f8(i64 %a, i64 %b) {
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; CHECK-LABEL: f8:
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; CHECK: risbg %r2, %r3, 8, 63, 56
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; CHECK: br %r14
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%anda = and i64 %a, -72057594037927936
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%shrb = lshr i64 %b, 8
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%or = or i64 %anda, %shrb
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ret i64 %or
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}
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110
test/CodeGen/SystemZ/rosbg-01.ll
Normal file
110
test/CodeGen/SystemZ/rosbg-01.ll
Normal file
@ -0,0 +1,110 @@
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; Test sequences that can use ROSBG.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test the simple case.
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define i32 @f1(i32 %a, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: rosbg %r2, %r3, 59, 59, 0
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; CHECK: br %r14
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%andb = and i32 %b, 16
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%or = or i32 %a, %andb
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ret i32 %or
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}
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; ...and again with i64.
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define i64 @f2(i64 %a, i64 %b) {
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; CHECK-LABEL: f2:
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; CHECK: rosbg %r2, %r3, 59, 59, 0
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; CHECK: br %r14
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%andb = and i64 %b, 16
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%or = or i64 %a, %andb
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ret i64 %or
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}
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; Test a case where wraparound is needed.
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define i32 @f3(i32 %a, i32 %b) {
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; CHECK-LABEL: f3:
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; CHECK: rosbg %r2, %r3, 63, 60, 0
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; CHECK: br %r14
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%andb = and i32 %b, -7
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%or = or i32 %a, %andb
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ret i32 %or
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}
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; ...and again with i64.
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define i64 @f4(i64 %a, i64 %b) {
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; CHECK-LABEL: f4:
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; CHECK: rosbg %r2, %r3, 63, 60, 0
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; CHECK: br %r14
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%andb = and i64 %b, -7
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%or = or i64 %a, %andb
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ret i64 %or
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}
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; Test a case with just a shift.
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define i32 @f6(i32 %a, i32 %b) {
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; CHECK-LABEL: f6:
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; CHECK: rosbg %r2, %r3, 32, 51, 12
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; CHECK: br %r14
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%shrb = shl i32 %b, 12
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%or = or i32 %a, %shrb
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ret i32 %or
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}
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; ...and again with i64.
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define i64 @f7(i64 %a, i64 %b) {
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; CHECK-LABEL: f7:
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; CHECK: rosbg %r2, %r3, 0, 51, 12
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; CHECK: br %r14
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%shrb = shl i64 %b, 12
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%or = or i64 %a, %shrb
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ret i64 %or
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}
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; Test a case with just a rotate. This can't use ROSBG.
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define i32 @f8(i32 %a, i32 %b) {
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; CHECK-LABEL: f8:
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; CHECK: rll {{%r[0-5]}}
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; CHECK: or {{%r[0-5]}}
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; CHECK: br %r14
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%shlb = shl i32 %b, 30
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%shrb = lshr i32 %b, 2
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%rotlb = or i32 %shlb, %shrb
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%or = or i32 %a, %rotlb
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ret i32 %or
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}
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; ...and again with i64, which can.
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define i64 @f9(i64 %a, i64 %b) {
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; CHECK-LABEL: f9:
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; CHECK: rosbg %r2, %r3, 0, 63, 47
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; CHECK: br %r14
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%shlb = shl i64 %b, 47
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%shrb = lshr i64 %b, 17
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%rotlb = or i64 %shlb, %shrb
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%or = or i64 %a, %rotlb
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ret i64 %or
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}
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; Test a case with a shift and AND.
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define i32 @f10(i32 %a, i32 %b) {
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; CHECK-LABEL: f10:
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; CHECK: rosbg %r2, %r3, 56, 59, 4
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; CHECK: br %r14
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%shrb = shl i32 %b, 4
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%andb = and i32 %shrb, 240
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%or = or i32 %a, %andb
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ret i32 %or
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}
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; ...and again with i64.
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define i64 @f11(i64 %a, i64 %b) {
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; CHECK-LABEL: f11:
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; CHECK: rosbg %r2, %r3, 56, 59, 4
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; CHECK: br %r14
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%shrb = shl i64 %b, 4
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%andb = and i64 %shrb, 240
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%or = or i64 %a, %andb
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ret i64 %or
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}
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