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R600/SI: Fix fneg for 0.0
V_ADD_F32 with source modifier does not produce -0.0 for this. Just manipulate the sign bit directly instead. Also add a pattern for (fneg (fabs ...)). Fixes a bunch of bit encoding piglit tests with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200743 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michel Danzer
parent
e2d1c6c19d
commit
de2e0bc366
@ -1688,16 +1688,30 @@ def : Pat <
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0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
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>;
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/********** ================================ **********/
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/********** Floating point absolute/negative **********/
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/********** ================================ **********/
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// Manipulate the sign bit directly, as e.g. using the source negation modifier
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// in V_ADD_F32_e64 $src, 0, [...] does not result in -0.0 for $src == +0.0,
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// breaking the piglit *s-floatBitsToInt-neg* tests
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// TODO: Look into not implementing isFNegFree/isFAbsFree for SI, and possibly
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// removing these patterns
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def : Pat <
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(fneg (fabs f32:$src)),
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(V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
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>;
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def : Pat <
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(fabs f32:$src),
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(V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
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1 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
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(V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff)) /* Clear sign bit */
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>;
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def : Pat <
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(fneg f32:$src),
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(V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
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0 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 1 /* NEG */)
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(V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Toggle sign bit */
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>;
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/********** ================== **********/
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@ -9,7 +9,7 @@
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; R600-CHECK-NOT: AND
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; R600-CHECK: |PV.{{[XYZW]}}|
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; SI-CHECK-LABEL: @fabs_free
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; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0
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; SI-CHECK: V_AND_B32
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define void @fabs_free(float addrspace(1)* %out, i32 %in) {
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entry:
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@ -23,8 +23,8 @@ entry:
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; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
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; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
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; SI-CHECK-LABEL: @fabs_v2
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; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0
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; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0
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; SI-CHECK: V_AND_B32
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; SI-CHECK: V_AND_B32
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define void @fabs_v2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
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entry:
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%0 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
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@ -38,10 +38,10 @@ entry:
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; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
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; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
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; SI-CHECK-LABEL: @fabs_v4
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; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0
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; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0
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; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0
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; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0
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; SI-CHECK: V_AND_B32
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; SI-CHECK: V_AND_B32
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; SI-CHECK: V_AND_B32
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; SI-CHECK: V_AND_B32
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define void @fabs_v4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
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entry:
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%0 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
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55
test/CodeGen/R600/fneg-fabs.ll
Normal file
55
test/CodeGen/R600/fneg-fabs.ll
Normal file
@ -0,0 +1,55 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
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; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
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; DAGCombiner will transform:
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; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF))
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; unless isFabsFree returns true
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; R600-CHECK-LABEL: @fneg_fabs_free
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; R600-CHECK-NOT: AND
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; R600-CHECK: |PV.{{[XYZW]}}|
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; R600-CHECK: -PV
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; SI-CHECK-LABEL: @fneg_fabs_free
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; SI-CHECK: V_OR_B32
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define void @fneg_fabs_free(float addrspace(1)* %out, i32 %in) {
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entry:
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%0 = bitcast i32 %in to float
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%1 = call float @fabs(float %0)
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%2 = fsub float -0.000000e+00, %1
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store float %2, float addrspace(1)* %out
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ret void
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}
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; R600-CHECK-LABEL: @fneg_fabs_v2
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; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
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; R600-CHECK: -PV
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; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
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; R600-CHECK: -PV
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; SI-CHECK-LABEL: @fneg_fabs_v2
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; SI-CHECK: V_OR_B32
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; SI-CHECK: V_OR_B32
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define void @fneg_fabs_v2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
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entry:
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%0 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
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%1 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %0
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store <2 x float> %1, <2 x float> addrspace(1)* %out
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ret void
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}
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; SI-CHECK-LABEL: @fneg_fabs_v4
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; SI-CHECK: V_OR_B32
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; SI-CHECK: V_OR_B32
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; SI-CHECK: V_OR_B32
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; SI-CHECK: V_OR_B32
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define void @fneg_fabs_v4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
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entry:
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%0 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
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%1 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %0
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store <4 x float> %1, <4 x float> addrspace(1)* %out
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ret void
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}
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declare float @fabs(float ) readnone
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declare <2 x float> @llvm.fabs.v2f32(<2 x float> ) readnone
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declare <4 x float> @llvm.fabs.v4f32(<4 x float> ) readnone
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@ -4,7 +4,7 @@
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; R600-CHECK-LABEL: @fneg
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; R600-CHECK: -PV
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; SI-CHECK-LABEL: @fneg
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; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
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; SI-CHECK: V_XOR_B32
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define void @fneg(float addrspace(1)* %out, float %in) {
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entry:
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%0 = fsub float -0.000000e+00, %in
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@ -16,8 +16,8 @@ entry:
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; R600-CHECK: -PV
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; R600-CHECK: -PV
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; SI-CHECK-LABEL: @fneg_v2
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; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
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; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
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; SI-CHECK: V_XOR_B32
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; SI-CHECK: V_XOR_B32
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define void @fneg_v2(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) {
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entry:
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%0 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in
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@ -31,10 +31,10 @@ entry:
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; R600-CHECK: -PV
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; R600-CHECK: -PV
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; SI-CHECK-LABEL: @fneg_v4
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; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
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; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
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; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
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; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
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; SI-CHECK: V_XOR_B32
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; SI-CHECK: V_XOR_B32
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; SI-CHECK: V_XOR_B32
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; SI-CHECK: V_XOR_B32
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define void @fneg_v4(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) {
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entry:
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%0 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in
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