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Tighten operand checking of register-shifted-register operands.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137180 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2011-08-09 23:33:27 +00:00
parent d40aa24ebf
commit de317f40f7
4 changed files with 7 additions and 9 deletions
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4
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@@ -683,8 +683,8 @@ static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
unsigned Rs = fieldFromInstruction32(Val, 8, 4);
// Register-register
DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
DecodeGPRRegisterClass(Inst, Rs, Address, Decoder);
if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false;
if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false;
ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
switch (type) {