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Make pseudos FEXT_CCRX16_ins and FEXT_CCRXI16_ins into custom emitters.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176007 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler 2013-02-25 02:25:47 +00:00
parent 6172f02983
commit de89ecd011
5 changed files with 70 additions and 69 deletions
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55
lib/Target/Mips/Mips16InstrInfo.cpp
View File

@ -138,18 +138,6 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
case Mips::RetRA16:
ExpandRetRA16(MBB, MI, Mips::JrcRa16);
break;
case Mips::SltCCRxRy16:
ExpandFEXT_CCRX16_ins(MBB, MI, Mips::SltRxRy16);
break;
case Mips::SltiCCRxImmX16:
ExpandFEXT_CCRXI16_ins(MBB, MI, Mips::SltiRxImm16, Mips::SltiRxImmX16);
break;
case Mips::SltiuCCRxImmX16:
ExpandFEXT_CCRXI16_ins(MBB, MI, Mips::SltiuRxImm16, Mips::SltiuRxImmX16);
break;
case Mips::SltuCCRxRy16:
ExpandFEXT_CCRX16_ins(MBB, MI, Mips::SltuRxRy16);
break;
}
MBB.erase(MI);
@ -411,29 +399,6 @@ void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
}
void Mips16InstrInfo::ExpandFEXT_CCRX16_ins(
MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SltOpc) const {
unsigned CC = I->getOperand(0).getReg();
unsigned regX = I->getOperand(1).getReg();
unsigned regY = I->getOperand(2).getReg();
BuildMI(MBB, I, I->getDebugLoc(), get(SltOpc)).addReg(regX).addReg(regY);
BuildMI(MBB, I, I->getDebugLoc(),
get(Mips::MoveR3216), CC).addReg(Mips::T8);
}
void Mips16InstrInfo::ExpandFEXT_CCRXI16_ins(
MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SltiOpc, unsigned SltiXOpc) const {
unsigned CC = I->getOperand(0).getReg();
unsigned regX = I->getOperand(1).getReg();
int64_t Imm = I->getOperand(2).getImm();
unsigned SltOpc = whichOp8u_or_16simm(SltiOpc, SltiXOpc, Imm);
BuildMI(MBB, I, I->getDebugLoc(), get(SltOpc)).addReg(regX).addImm(Imm);
BuildMI(MBB, I, I->getDebugLoc(),
get(Mips::MoveR3216), CC).addReg(Mips::T8);
}
const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
if (validSpImm8(Imm))
@ -448,26 +413,6 @@ void Mips16InstrInfo::BuildAddiuSpImm
BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
}
unsigned Mips16InstrInfo::whichOp8_or_16uimm
(unsigned shortOp, unsigned longOp, int64_t Imm) {
if (isUInt<8>(Imm))
return shortOp;
else if (isUInt<16>(Imm))
return longOp;
else
llvm_unreachable("immediate field not usable");
}
unsigned Mips16InstrInfo::whichOp8u_or_16simm
(unsigned shortOp, unsigned longOp, int64_t Imm) {
if (isUInt<8>(Imm))
return shortOp;
else if (isInt<16>(Imm))
return longOp;
else
llvm_unreachable("immediate field not usable");
}
const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
return new Mips16InstrInfo(TM);
}

14
lib/Target/Mips/Mips16InstrInfo.h
View File

@ -115,20 +115,6 @@ private:
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const;
void ExpandFEXT_CCRX16_ins(
MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SltOpc) const;
void ExpandFEXT_CCRXI16_ins(
MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SltiOpc, unsigned SltiXOpc) const;
static unsigned
whichOp8_or_16uimm (unsigned shortOp, unsigned longOp, int64_t Imm);
static unsigned
whichOp8u_or_16simm (unsigned shortOp, unsigned longOp, int64_t Imm);
};
}

2
lib/Target/Mips/Mips16InstrInfo.td
View File

@ -90,6 +90,7 @@ class FEXT_CCRXI16_ins<string asmstr>:
MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
!strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> {
let isCodeGenOnly=1;
let usesCustomInserter = 1;
}
// JAL and JALX instruction format
@ -138,6 +139,7 @@ class FCCRR16_ins<string asmstr> :
MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
!strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
let isCodeGenOnly=1;
let usesCustomInserter = 1;
}
//

61
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -1434,6 +1434,8 @@ MachineBasicBlock
*MipsTargetLowering::EmitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
MachineInstr *MI,
MachineBasicBlock *BB) const {
if (DontExpandCondPseudos16)
return BB;
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
unsigned regX = MI->getOperand(0).getReg();
unsigned regY = MI->getOperand(1).getReg();
@ -1448,6 +1450,8 @@ MachineBasicBlock
MachineBasicBlock *MipsTargetLowering::EmitFEXT_T8I8I16_ins(
unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc,
MachineInstr *MI, MachineBasicBlock *BB) const {
if (DontExpandCondPseudos16)
return BB;
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
unsigned regX = MI->getOperand(0).getReg();
int64_t imm = MI->getOperand(1).getImm();
@ -1465,6 +1469,51 @@ MachineBasicBlock *MipsTargetLowering::EmitFEXT_T8I8I16_ins(
return BB;
}
static unsigned Mips16WhichOp8uOr16simm
(unsigned shortOp, unsigned longOp, int64_t Imm) {
if (isUInt<8>(Imm))
return shortOp;
else if (isInt<16>(Imm))
return longOp;
else
llvm_unreachable("immediate field not usable");
}
MachineBasicBlock *MipsTargetLowering::EmitFEXT_CCRX16_ins(
unsigned SltOpc,
MachineInstr *MI, MachineBasicBlock *BB) const {
if (DontExpandCondPseudos16)
return BB;
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
unsigned CC = MI->getOperand(0).getReg();
unsigned regX = MI->getOperand(1).getReg();
unsigned regY = MI->getOperand(2).getReg();
BuildMI(*BB, MI, MI->getDebugLoc(),
TII->get(SltOpc)).addReg(regX).addReg(regY);
BuildMI(*BB, MI, MI->getDebugLoc(),
TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
MachineBasicBlock *MipsTargetLowering::EmitFEXT_CCRXI16_ins(
unsigned SltiOpc, unsigned SltiXOpc,
MachineInstr *MI, MachineBasicBlock *BB )const {
if (DontExpandCondPseudos16)
return BB;
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
unsigned CC = MI->getOperand(0).getReg();
unsigned regX = MI->getOperand(1).getReg();
int64_t Imm = MI->getOperand(2).getImm();
unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
BuildMI(*BB, MI, MI->getDebugLoc(),
TII->get(SltOpc)).addReg(regX).addImm(Imm);
BuildMI(*BB, MI, MI->getDebugLoc(),
TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
MachineBasicBlock *
MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *BB) const {
@ -1633,6 +1682,18 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
case Mips::BtnezT8SltiuX16: return EmitFEXT_T8I8I16_ins(
Mips::BtnezX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
break;
case Mips::SltCCRxRy16:
return EmitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB);
break;
case Mips::SltiCCRxImmX16:
return EmitFEXT_CCRXI16_ins
(Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
case Mips::SltiuCCRxImmX16:
return EmitFEXT_CCRXI16_ins
(Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
case Mips::SltuCCRxRy16:
return EmitFEXT_CCRX16_ins
(Mips::SltuRxRy16, MI, BB);
}
}

7
lib/Target/Mips/MipsISelLowering.h
View File

@ -419,6 +419,13 @@ namespace llvm {
MachineBasicBlock *EmitFEXT_T8I8I16_ins(
unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc,
MachineInstr *MI, MachineBasicBlock *BB) const;
MachineBasicBlock *EmitFEXT_CCRX16_ins(
unsigned SltOpc,
MachineInstr *MI, MachineBasicBlock *BB) const;
MachineBasicBlock *EmitFEXT_CCRXI16_ins(
unsigned SltiOpc, unsigned SltiXOpc,
MachineInstr *MI, MachineBasicBlock *BB )const;
};
}