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Also inflate register classes around inline asm.
Now that MI->getRegClassConstraint() can also handle inline assembly, don't bail when recomputing the register class of a virtual register used by inline asm. This fixes PR11078. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141836 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -79,11 +79,8 @@ MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
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// TRI doesn't have accurate enough information to model this yet.
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if (I.getOperand().getSubReg())
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return false;
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// Inline asm instuctions don't remember their constraints.
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if (I->isInlineAsm())
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return false;
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const TargetRegisterClass *OpRC =
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TII->getRegClass(I->getDesc(), I.getOperandNo(), TRI);
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I->getRegClassConstraint(I.getOperandNo(), TII, TRI);
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if (OpRC)
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NewRC = TRI->getCommonSubClass(NewRC, OpRC);
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if (!NewRC || NewRC == OldRC)
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@ -364,3 +364,30 @@ entry:
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"5":
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ret void
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}
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; PR11078
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;
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; A virtual register used by the "foo" inline asm memory operand gets
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; constrained to GR32_ABCD during coalescing. This makes the inline asm
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; impossible to allocate without splitting the live range and reinflating the
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; register class around the inline asm.
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;
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; The constraint originally comes from the TEST8ri optimization of (icmp (and %t0, 1), 0).
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@__force_order = external hidden global i32, align 4
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define void @pr11078(i32* %pgd) nounwind {
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entry:
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%t0 = load i32* %pgd, align 4
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%and2 = and i32 %t0, 1
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%tobool = icmp eq i32 %and2, 0
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br i1 %tobool, label %if.then, label %if.end
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if.then:
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%t1 = tail call i32 asm sideeffect "bar", "=r,=*m,~{dirflag},~{fpsr},~{flags}"(i32* @__force_order) nounwind
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br label %if.end
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if.end:
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%t6 = inttoptr i32 %t0 to i64*
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%t11 = tail call i64 asm sideeffect "foo", "=*m,=A,{bx},{cx},1,~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %t6, i32 0, i32 0, i64 0) nounwind
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ret void
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}
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