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Re-commit r235560: Switch lowering: extract jump tables and bit tests before building binary tree (PR22262)
Third time's the charm. The previous commit was reverted as a reverse for-loop in SelectionDAGBuilder::lowerWorkItem did 'I--' on an iterator at the beginning of a vector, causing asserts when using debugging iterators. This commit fixes that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235608 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hans Wennborg
@@ -1,4 +1,4 @@
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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@@ -45,4 +45,37 @@ if.end3: ; preds = %if.then, %if.then2,
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; CHECK: blr
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}
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@.str0 = private unnamed_addr constant [2 x i8] c"a\00"
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@.str1 = private unnamed_addr constant [2 x i8] c"b\00"
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@.str2 = private unnamed_addr constant [2 x i8] c"c\00"
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@.str3 = private unnamed_addr constant [2 x i8] c"d\00"
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@.str4 = private unnamed_addr constant [2 x i8] c"e\00"
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define i8* @dont_assert(i32 %x) {
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; LLVM would assert due to moving an early return into the jump table block and
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; removing one of its predecessors despite that block ending with an indirect
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; branch.
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entry:
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switch i32 %x, label %sw.epilog [
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i32 1, label %return
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i32 2, label %sw.bb1
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i32 3, label %sw.bb2
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i32 4, label %sw.bb3
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i32 255, label %sw.bb4
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]
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sw.bb1: br label %return
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sw.bb2: br label %return
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sw.bb3: br label %return
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sw.bb4: br label %return
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sw.epilog: br label %return
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return:
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%retval.0 = phi i8* [ null, %sw.epilog ],
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[ getelementptr inbounds ([2 x i8], [2 x i8]* @.str4, i64 0, i64 0), %sw.bb4 ],
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[ getelementptr inbounds ([2 x i8], [2 x i8]* @.str3, i64 0, i64 0), %sw.bb3 ],
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[ getelementptr inbounds ([2 x i8], [2 x i8]* @.str2, i64 0, i64 0), %sw.bb2 ],
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[ getelementptr inbounds ([2 x i8], [2 x i8]* @.str1, i64 0, i64 0), %sw.bb1 ],
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[ getelementptr inbounds ([2 x i8], [2 x i8]* @.str0, i64 0, i64 0), %entry ]
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ret i8* %retval.0
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}
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attributes #0 = { nounwind }
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@@ -1,5 +1,5 @@
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; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
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; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s
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; RUN: llc -mcpu=pwr7 -code-model=medium <%s | FileCheck %s
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; RUN: llc -mcpu=pwr7 -code-model=large <%s | FileCheck %s
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; Test correct code generation for medium and large code model
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; for loading the address of a jump table from the TOC.
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@@ -3,6 +3,12 @@
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; RUN: llc -O0 -mcpu=pwr7 -code-model=large -filetype=obj -fast-isel=false %s -o - | \
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; RUN: llvm-readobj -r | FileCheck -check-prefix=LARGE %s
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; Run jump table test separately since jump tables aren't generated at -O0.
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; RUN: llc -mcpu=pwr7 -code-model=medium -filetype=obj -fast-isel=false %s -o - | \
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; RUN: llvm-readobj -r | FileCheck -check-prefix=MEDIUM-JT %s
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; RUN: llc -mcpu=pwr7 -code-model=large -filetype=obj -fast-isel=false %s -o - | \
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; RUN: llvm-readobj -r | FileCheck -check-prefix=LARGE-JT %s
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; FIXME: When asm-parse is available, could make this an assembly test.
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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@@ -92,6 +98,46 @@ entry:
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]]
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM4]]
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@ti = common global i32 0, align 4
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define signext i32 @test_tentative() nounwind {
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entry:
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%0 = load i32, i32* @ti, align 4
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%inc = add nsw i32 %0, 1
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store i32 %inc, i32* @ti, align 4
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ret i32 %0
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}
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; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
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; accessing tentatively declared variable ti.
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;
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]]
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;
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]]
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define i8* @test_fnaddr() nounwind {
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entry:
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%func = alloca i32 (i32)*, align 8
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store i32 (i32)* @foo, i32 (i32)** %func, align 8
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%0 = load i32 (i32)*, i32 (i32)** %func, align 8
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%1 = bitcast i32 (i32)* %0 to i8*
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ret i8* %1
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}
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declare signext i32 @foo(i32 signext)
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; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
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; accessing function address foo.
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;
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM7:[^ ]+]]
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM7]]
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;
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM7:[^ ]+]]
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM7]]
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define signext i32 @test_jump_table(i32 signext %i) nounwind {
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entry:
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%i.addr = alloca i32, align 4
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@@ -139,47 +185,12 @@ sw.epilog: ; preds = %sw.bb3, %sw.default
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; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
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; accessing a jump table address.
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;
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM5:[^ ]+]]
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM5]]
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; MEDIUM-JT: Relocations [
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; MEDIUM-JT: Section ({{.*}}) .rela.text {
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; MEDIUM-JT-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM:[^ ]+]]
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; MEDIUM-JT-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM]]
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;
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM5:[^ ]+]]
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM5]]
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@ti = common global i32 0, align 4
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define signext i32 @test_tentative() nounwind {
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entry:
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%0 = load i32, i32* @ti, align 4
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%inc = add nsw i32 %0, 1
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store i32 %inc, i32* @ti, align 4
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ret i32 %0
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}
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; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
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; accessing tentatively declared variable ti.
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;
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]]
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;
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]]
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define i8* @test_fnaddr() nounwind {
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entry:
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%func = alloca i32 (i32)*, align 8
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store i32 (i32)* @foo, i32 (i32)** %func, align 8
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%0 = load i32 (i32)*, i32 (i32)** %func, align 8
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%1 = bitcast i32 (i32)* %0 to i8*
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ret i8* %1
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}
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declare signext i32 @foo(i32 signext)
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; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
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; accessing function address foo.
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;
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM7:[^ ]+]]
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM7]]
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;
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM7:[^ ]+]]
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM7]]
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; LARGE-JT: Relocations [
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; LARGE-JT: Section ({{.*}}) .rela.text {
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; LARGE-JT-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM:[^ ]+]]
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; LARGE-JT-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM]]
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