Make reg. numbers signed ints.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1137 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve 2001-11-05 03:56:02 +00:00
parent 0b12f2bb30
commit df1c3b8398
2 changed files with 6 additions and 6 deletions

View File

@ -107,9 +107,9 @@ public:
opType == MO_PCRelativeDisp); opType == MO_PCRelativeDisp);
return value; return value;
} }
inline unsigned int getMachineRegNum() const { inline int getMachineRegNum() const {
assert(opType == MO_MachineRegister); assert(opType == MO_MachineRegister);
return (unsigned) regNum; return regNum;
} }
inline int64_t getImmedValue () const { inline int64_t getImmedValue () const {
assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed); assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
@ -132,7 +132,7 @@ private:
Value* _val); Value* _val);
void InitializeConst (MachineOperandType operandType, void InitializeConst (MachineOperandType operandType,
int64_t intValue); int64_t intValue);
void InitializeReg (unsigned int regNum); void InitializeReg (int regNum);
friend class MachineInstr; friend class MachineInstr;
friend class ValOpIterator<const MachineInstr, const Value>; friend class ValOpIterator<const MachineInstr, const Value>;
@ -215,7 +215,7 @@ MachineOperand::InitializeConst(MachineOperandType operandType,
} }
inline void inline void
MachineOperand::InitializeReg(unsigned int _regNum) MachineOperand::InitializeReg(int _regNum)
{ {
opType = MO_MachineRegister; opType = MO_MachineRegister;
value = NULL; value = NULL;
@ -309,7 +309,7 @@ public:
MachineOperand::MachineOperandType operandType, MachineOperand::MachineOperandType operandType,
int64_t intValue, bool isDef=false); int64_t intValue, bool isDef=false);
void SetMachineOperand(unsigned int i, void SetMachineOperand(unsigned int i,
unsigned int regNum, int regNum,
bool isDef=false); bool isDef=false);
void addImplicitRef (Value* val, void addImplicitRef (Value* val,

View File

@ -66,7 +66,7 @@ MachineInstr::SetMachineOperand(unsigned int i,
void void
MachineInstr::SetMachineOperand(unsigned int i, MachineInstr::SetMachineOperand(unsigned int i,
unsigned int regNum, bool isdef=false) int regNum, bool isdef=false)
{ {
assert(i < operands.size()); assert(i < operands.size());
operands[i].InitializeReg(regNum); operands[i].InitializeReg(regNum);