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https://github.com/c64scene-ar/llvm-6502.git
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[Hexagon] Removing old newvalue store variants. Adding postincrement immediate newvalue stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225009 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
25547ee83c
commit
df2531486d
@ -655,15 +655,15 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
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return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
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case Hexagon::S2_storeri_io:
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case Hexagon::STriw_nv_V4:
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case Hexagon::S2_storerinew_io:
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return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
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case Hexagon::S2_storerh_io:
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case Hexagon::STrih_nv_V4:
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case Hexagon::S2_storerhnew_io:
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return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
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case Hexagon::S2_storerb_io:
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case Hexagon::STrib_nv_V4:
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case Hexagon::S2_storerbnew_io:
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return isUInt<6>(MI->getOperand(1).getImm());
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case Hexagon::L2_loadrd_io:
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@ -1556,10 +1556,10 @@ int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
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return Hexagon::STrih_shl_nv_V4;
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case Hexagon::STriw_f:
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return Hexagon::STriw_nv_V4;
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return Hexagon::S2_storerinew_io;
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case Hexagon::STriw_indexed_f:
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return Hexagon::S2_storerinew_io;
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return Hexagon::S4_storerinew_rr;
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case Hexagon::STriw_shl_V4:
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return Hexagon::STriw_shl_nv_V4;
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@ -1210,113 +1210,107 @@ let addrMode = BaseImmOffset, InputType = "imm", isCodeGenOnly = 0 in {
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u6_2Ext, 0b10>, AddrModeRel;
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}
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// multiclass for new-value store instructions with base + immediate offset.
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// and MEMri operand.
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multiclass ST_MEMri_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
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bit isPredNew> {
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let isPredicatedNew = isPredNew in
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def NAME#_nv_V4 : NVInst_V4<(outs),
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(ins PredRegs:$src1, MEMri:$addr, RC: $src2),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#mnemonic#"($addr) = $src2.new",
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[]>,
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Requires<[HasV4T]>;
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}
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multiclass ST_MEMri_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
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let isPredicatedFalse = PredNot in {
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defm _c#NAME : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 0>;
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// Predicate new
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defm _cdn#NAME : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 1>;
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}
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}
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let mayStore = 1, isNVStore = 1, isExtendable = 1, hasSideEffects = 0 in
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multiclass ST_MEMri_nv<string mnemonic, string CextOp, RegisterClass RC,
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bits<5> ImmBits, bits<5> PredImmBits> {
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let CextOpcode = CextOp, BaseOpcode = CextOp in {
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let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
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isPredicable = 1 in
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def NAME#_nv_V4 : NVInst_V4<(outs),
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(ins MEMri:$addr, RC:$src),
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mnemonic#"($addr) = $src.new",
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[]>,
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Requires<[HasV4T]>;
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let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
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hasSideEffects = 0, isPredicated = 1 in {
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defm Pt : ST_MEMri_Pred_nv<mnemonic, RC, 0>;
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defm NotPt : ST_MEMri_Pred_nv<mnemonic, RC, 1>;
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}
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}
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}
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let addrMode = BaseImmOffset, isMEMri = "true", validSubTargets = HasV4SubT,
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mayStore = 1 in {
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let accessSize = ByteAccess in
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defm STrib: ST_MEMri_nv<"memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
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let accessSize = HalfWordAccess in
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defm STrih: ST_MEMri_nv<"memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
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let accessSize = WordAccess in
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defm STriw: ST_MEMri_nv<"memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
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}
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//===----------------------------------------------------------------------===//
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// Post increment store
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// Template class for non-predicated post increment .new stores
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// mem[bhwd](Rx++#s4:[0123])=Nt.new
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//===----------------------------------------------------------------------===//
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let isPredicable = 1, hasSideEffects = 0, validSubTargets = HasV4SubT,
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addrMode = PostInc, isNVStore = 1, isNewValue = 1, opNewValue = 3 in
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class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
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: NVInstPI_V4 <(outs IntRegs:$_dst_),
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(ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
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mnemonic#"($src1++#$offset) = $src2.new",
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[], "$src1 = $_dst_">,
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AddrModeRel {
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bits<5> src1;
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bits<3> src2;
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bits<7> offset;
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bits<4> offsetBits;
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multiclass ST_PostInc_Pbase_nv<string mnemonic, RegisterClass RC, Operand ImmOp,
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bit isNot, bit isPredNew> {
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let isPredicatedNew = isPredNew in
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def NAME#_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#mnemonic#"($src2++#$offset) = $src3.new",
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[],
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"$src2 = $dst">,
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Requires<[HasV4T]>;
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}
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string ImmOpStr = !cast<string>(ImmOp);
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let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
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!if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
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/* s4_0Imm */ offset{3-0}));
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let IClass = 0b1010;
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multiclass ST_PostInc_Pred_nv<string mnemonic, RegisterClass RC,
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Operand ImmOp, bit PredNot> {
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let isPredicatedFalse = PredNot in {
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defm _c#NAME : ST_PostInc_Pbase_nv<mnemonic, RC, ImmOp, PredNot, 0>;
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// Predicate new
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let Predicates = [HasV4T], validSubTargets = HasV4SubT in
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defm _cdn#NAME : ST_PostInc_Pbase_nv<mnemonic, RC, ImmOp, PredNot, 1>;
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let Inst{27-21} = 0b1011101;
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let Inst{20-16} = src1;
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let Inst{13} = 0b0;
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let Inst{12-11} = MajOp;
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let Inst{10-8} = src2;
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let Inst{7} = 0b0;
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let Inst{6-3} = offsetBits;
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let Inst{1} = 0b0;
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}
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//===----------------------------------------------------------------------===//
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// Template class for predicated post increment .new stores
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// if([!]Pv[.new]) mem[bhwd](Rx++#s4:[0123])=Nt.new
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//===----------------------------------------------------------------------===//
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let isPredicated = 1, hasSideEffects = 0, validSubTargets = HasV4SubT,
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addrMode = PostInc, isNVStore = 1, isNewValue = 1, opNewValue = 4 in
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class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
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bits<2> MajOp, bit isPredNot, bit isPredNew >
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: NVInstPI_V4 <(outs IntRegs:$_dst_),
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(ins PredRegs:$src1, IntRegs:$src2,
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ImmOp:$offset, IntRegs:$src3),
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!if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#mnemonic#"($src2++#$offset) = $src3.new",
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[], "$src2 = $_dst_">,
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AddrModeRel {
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bits<2> src1;
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bits<5> src2;
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bits<3> src3;
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bits<7> offset;
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bits<4> offsetBits;
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string ImmOpStr = !cast<string>(ImmOp);
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let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
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!if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
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/* s4_0Imm */ offset{3-0}));
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let isPredicatedNew = isPredNew;
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let isPredicatedFalse = isPredNot;
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let IClass = 0b1010;
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let Inst{27-21} = 0b1011101;
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let Inst{20-16} = src2;
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let Inst{13} = 0b1;
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let Inst{12-11} = MajOp;
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let Inst{10-8} = src3;
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let Inst{7} = isPredNew;
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let Inst{6-3} = offsetBits;
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let Inst{2} = isPredNot;
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let Inst{1-0} = src1;
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}
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multiclass ST_PostInc_Pred_nv<string mnemonic, Operand ImmOp,
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bits<2> MajOp, bit PredNot> {
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def _pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 0>;
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// Predicate new
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def new_pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 1>;
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}
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let hasCtrlDep = 1, isNVStore = 1, hasSideEffects = 0 in
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multiclass ST_PostInc_nv<string mnemonic, string BaseOp, RegisterClass RC,
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Operand ImmOp> {
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multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp,
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bits<2> MajOp> {
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let BaseOpcode = "POST_"#BaseOp in {
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let isPredicable = 1 in
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def NAME#_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
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(ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
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mnemonic#"($src1++#$offset) = $src2.new",
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[],
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"$src1 = $dst">,
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Requires<[HasV4T]>;
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def S2_#NAME#_pi : T_StorePI_nv <mnemonic, ImmOp, MajOp>;
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let isPredicated = 1 in {
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defm Pt : ST_PostInc_Pred_nv<mnemonic, RC, ImmOp, 0 >;
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defm NotPt : ST_PostInc_Pred_nv<mnemonic, RC, ImmOp, 1 >;
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}
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// Predicated
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defm S2_p#NAME#t : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 0>;
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defm S2_p#NAME#f : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 1>;
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}
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}
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let addrMode = PostInc, validSubTargets = HasV4SubT in {
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defm POST_STbri: ST_PostInc_nv <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
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defm POST_SThri: ST_PostInc_nv <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
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defm POST_STwri: ST_PostInc_nv <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
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}
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let accessSize = ByteAccess, isCodeGenOnly = 0 in
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defm storerbnew: ST_PostInc_nv <"memb", "STrib", s4_0Imm, 0b00>;
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let accessSize = HalfWordAccess, isCodeGenOnly = 0 in
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defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>;
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let accessSize = WordAccess, isCodeGenOnly = 0 in
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defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>;
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// memb(Rx++#s4:0:circ(Mu))=Nt.new
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// memb(Rx++I:circ(Mu))=Nt.new
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@ -6,6 +6,9 @@
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0x1f 0x40 0x7f 0x70 0x15 0xc2 0xb1 0xa1
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# CHECK: r31 = r31
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# CHECK-NEXT: memb(r17+#21) = r2.new
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0x1f 0x40 0x7f 0x70 0x28 0xc2 0xb1 0xab
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# CHECK: r31 = r31
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# CHECK-NEXT: memb(r17++#5) = r2.new
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0x1f 0x40 0x7f 0x70 0xe2 0xf5 0xb1 0x34
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# CHECK: r31 = r31
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# CHECK-NEXT: if (p3) memb(r17+r21<<#3) = r2.new
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@ -34,6 +37,20 @@
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# CHECK: p3 = r5
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# CHECK-NEXT: r31 = r31
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# CHECK-NEXT: if (!p3.new) memb(r17+#21) = r2.new
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0x1f 0x40 0x7f 0x70 0x2b 0xe2 0xb1 0xab
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# CHECK: r31 = r31
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# CHECK-NEXT: if (p3) memb(r17++#5) = r2.new
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0x1f 0x40 0x7f 0x70 0x2f 0xe2 0xb1 0xab
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# CHECK: r31 = r31
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# CHECK-NEXT: if (!p3) memb(r17++#5) = r2.new
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0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xe2 0xb1 0xab
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# CHECK: p3 = r5
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# CHECK-NEXT: r31 = r31
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# CHECK-NEXT: if (p3.new) memb(r17++#5) = r2.new
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0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xaf 0xe2 0xb1 0xab
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# CHECK: p3 = r5
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# CHECK-NEXT: r31 = r31
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# CHECK-NEXT: if (!p3.new) memb(r17++#5) = r2.new
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0x1f 0x40 0x7f 0x70 0x8a 0xf5 0xb1 0x3b
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# CHECK: r31 = r31
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@ -41,6 +58,9 @@
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0x1f 0x40 0x7f 0x70 0x15 0xca 0xb1 0xa1
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# CHECK: r31 = r31
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# CHECK-NEXT: memh(r17+#42) = r2.new
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0x1f 0x40 0x7f 0x70 0x28 0xca 0xb1 0xab
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# CHECK: r31 = r31
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# CHECK-NEXT: memh(r17++#10) = r2.new
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0x1f 0x40 0x7f 0x70 0xea 0xf5 0xb1 0x34
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# CHECK: r31 = r31
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# CHECK-NEXT: if (p3) memh(r17+r21<<#3) = r2.new
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@ -69,6 +89,20 @@
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# CHECK: p3 = r5
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# CHECK-NEXT: r31 = r31
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# CHECK-NEXT: if (!p3.new) memh(r17+#42) = r2.new
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0x1f 0x40 0x7f 0x70 0x2b 0xea 0xb1 0xab
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# CHECK: r31 = r31
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# CHECK-NEXT: if (p3) memh(r17++#10) = r2.new
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0x1f 0x40 0x7f 0x70 0x2f 0xea 0xb1 0xab
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# CHECK: r31 = r31
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# CHECK-NEXT: if (!p3) memh(r17++#10) = r2.new
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0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xea 0xb1 0xab
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# CHECK: p3 = r5
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# CHECK-NEXT: r31 = r31
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# CHECK-NEXT: if (p3.new) memh(r17++#10) = r2.new
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0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xaf 0xea 0xb1 0xab
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# CHECK: p3 = r5
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# CHECK-NEXT: r31 = r31
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# CHECK-NEXT: if (!p3.new) memh(r17++#10) = r2.new
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0x1f 0x40 0x7f 0x70 0x92 0xf5 0xb1 0x3b
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# CHECK: r31 = r31
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@ -76,6 +110,9 @@
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0x1f 0x40 0x7f 0x70 0x15 0xd2 0xb1 0xa1
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# CHECK: r31 = r31
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# CHECK-NEXT: memw(r17+#84) = r2.new
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0x1f 0x40 0x7f 0x70 0x28 0xd2 0xb1 0xab
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# CHECK: r31 = r31
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# CHECK-NEXT: memw(r17++#20) = r2.new
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0x1f 0x40 0x7f 0x70 0xf2 0xf5 0xb1 0x34
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# CHECK: r31 = r31
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# CHECK-NEXT: if (p3) memw(r17+r21<<#3) = r2.new
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@ -104,3 +141,17 @@
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# CHECK: p3 = r5
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# CHECK-NEXT: r31 = r31
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# CHECK-NEXT: if (!p3.new) memw(r17+#84) = r2.new
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0x1f 0x40 0x7f 0x70 0x2b 0xf2 0xb1 0xab
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# CHECK: r31 = r31
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# CHECK-NEXT: if (p3) memw(r17++#20) = r2.new
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0x1f 0x40 0x7f 0x70 0x2f 0xf2 0xb1 0xab
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# CHECK: r31 = r31
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# CHECK-NEXT: if (!p3) memw(r17++#20) = r2.new
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0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xf2 0xb1 0xab
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# CHECK: p3 = r5
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# CHECK-NEXT: r31 = r31
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# CHECK-NEXT: if (p3.new) memw(r17++#20) = r2.new
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0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xaf 0xf2 0xb1 0xab
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# CHECK: p3 = r5
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# CHECK-NEXT: r31 = r31
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# CHECK-NEXT: if (!p3.new) memw(r17++#20) = r2.new
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