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Assumption that "VectorizedValue" will always be an Instruction is not correct.
It can be a constant or a vector argument. ex : define i32 @hadd(<4 x i32> %a) #0 { entry: %vecext = extractelement <4 x i32> %a, i32 0 %vecext1 = extractelement <4 x i32> %a, i32 1 %add = add i32 %vecext, %vecext1 %vecext2 = extractelement <4 x i32> %a, i32 2 %add3 = add i32 %add, %vecext2 %vecext4 = extractelement <4 x i32> %a, i32 3 %add5 = add i32 %add3, %vecext4 ret i32 %add5 } git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225517 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3502,11 +3502,10 @@ private:
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/// \brief Emit a horizontal reduction of the vectorized value.
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/// \brief Emit a horizontal reduction of the vectorized value.
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Value *emitReduction(Value *VectorizedValue, IRBuilder<> &Builder) {
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Value *emitReduction(Value *VectorizedValue, IRBuilder<> &Builder) {
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assert(VectorizedValue && "Need to have a vectorized tree node");
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assert(VectorizedValue && "Need to have a vectorized tree node");
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Instruction *ValToReduce = dyn_cast<Instruction>(VectorizedValue);
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assert(isPowerOf2_32(ReduxWidth) &&
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assert(isPowerOf2_32(ReduxWidth) &&
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"We only handle power-of-two reductions for now");
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"We only handle power-of-two reductions for now");
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Value *TmpVec = ValToReduce;
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Value *TmpVec = VectorizedValue;
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for (unsigned i = ReduxWidth / 2; i != 0; i >>= 1) {
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for (unsigned i = ReduxWidth / 2; i != 0; i >>= 1) {
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if (IsPairwiseReduction) {
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if (IsPairwiseReduction) {
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Value *LeftMask =
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Value *LeftMask =
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