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CriticalAntiDepBreaker is no longer needed for armv7 scheduling.

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This is being disabled because it is no longer needed for
performance. It is only used by postRAscheduler which is also planned
for removal, and it is implemented with an out-dated view of register
liveness. It consideres aliases instead of register units, assumes
valid kill flags, and assumes implicit uses on partial register
defs. Kill flags and implicit operands are error prone and impossible
to verify. We should gradually eliminate dependence on them in the
postRA phases.

Targets that still benefit from this should move to the MI
scheduler. If that doesn't solve the problem, then we should add a
hook to regalloc to optimize reload placement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191348 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2013-09-25 00:26:16 +00:00
parent a26f428382
commit dfca6eec31
4 changed files with 6 additions and 8 deletions
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4
lib/Target/ARM/ARMSubtarget.cpp
View File

@ -282,8 +282,6 @@ bool ARMSubtarget::enablePostRAScheduler(
CodeGenOpt::Level OptLevel,
TargetSubtargetInfo::AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const {
Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
CriticalPathRCs.clear();
CriticalPathRCs.push_back(&ARM::GPRRegClass);
Mode = TargetSubtargetInfo::ANTIDEP_NONE;
return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
}

4
test/CodeGen/ARM/2011-10-26-memset-inline.ll
View File

@ -10,8 +10,8 @@ target triple = "thumbv7-apple-ios5.0.0"
; CHECK-GENERIT-NEXT: strb
; CHECK-GENERIT-NEXT: strb
; CHECK-GENERIT-NEXT: strb
; CHECK-UNALIGNED: strb
; CHECK-UNALIGNED-NEXT: str
; CHECK-UNALIGNED: strb
; CHECK-UNALIGNED: str
define void @foo(i8* nocapture %c) nounwind optsize {
entry:
call void @llvm.memset.p0i8.i64(i8* %c, i8 -1, i64 5, i32 1, i1 false)

4
test/CodeGen/ARM/2011-10-26-memset-with-neon.ll
View File

@ -1,8 +1,8 @@
; RUN: llc -march=arm -mcpu=cortex-a8 < %s | FileCheck %s
; Trigger multiple NEON stores.
; CHECK: vst1.64
; CHECK-NEXT: vst1.64
; CHECK: vst1.64
; CHECK: vst1.64
define void @f_0_40(i8* nocapture %c) nounwind optsize {
entry:
call void @llvm.memset.p0i8.i64(i8* %c, i8 0, i64 40, i32 16, i1 false)

2
test/CodeGen/ARM/vstlane.ll
View File

@ -13,7 +13,7 @@ define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind {
;Check for a post-increment updating store.
define void @vst1lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
;CHECK-LABEL: vst1lanei8_update:
;CHECK: vst1.8 {d16[3]}, [r2]!
;CHECK: vst1.8 {d16[3]}, [{{r[0-9]}}]!
%A = load i8** %ptr
%tmp1 = load <8 x i8>* %B
%tmp2 = extractelement <8 x i8> %tmp1, i32 3