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https://github.com/c64scene-ar/llvm-6502.git
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Make x86 fast-isel correctly choose between aligned and unaligned operations for vector stores. Fixes PR16640.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186491 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
d055c59544
commit
e0364b64d1
@ -79,8 +79,10 @@ private:
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bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR);
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bool X86FastEmitStore(EVT VT, const Value *Val, const X86AddressMode &AM);
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bool X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM);
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bool X86FastEmitStore(EVT VT, const Value *Val, const X86AddressMode &AM,
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bool Aligned = false);
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bool X86FastEmitStore(EVT VT, unsigned ValReg, const X86AddressMode &AM,
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bool Aligned = false);
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bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
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unsigned &ResultReg);
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@ -233,7 +235,8 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM,
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/// and a displacement offset, or a GlobalAddress,
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/// i.e. V. Return true if it is possible.
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bool
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X86FastISel::X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM) {
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X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg,
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const X86AddressMode &AM, bool Aligned) {
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// Get opcode and regclass of the output for the given store instruction.
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unsigned Opc = 0;
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switch (VT.getSimpleVT().SimpleTy) {
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@ -243,8 +246,8 @@ X86FastISel::X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM) {
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// Mask out all but lowest bit.
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unsigned AndResult = createResultReg(&X86::GR8RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1);
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Val = AndResult;
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TII.get(X86::AND8ri), AndResult).addReg(ValReg).addImm(1);
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ValReg = AndResult;
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}
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// FALLTHROUGH, handling i1 as i8.
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case MVT::i8: Opc = X86::MOV8mr; break;
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@ -260,26 +263,35 @@ X86FastISel::X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM) {
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(Subtarget->hasAVX() ? X86::VMOVSDmr : X86::MOVSDmr) : X86::ST_Fp64m;
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break;
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case MVT::v4f32:
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Opc = X86::MOVAPSmr;
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if (Aligned)
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Opc = X86::MOVAPSmr;
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else
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Opc = X86::MOVUPSmr;
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break;
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case MVT::v2f64:
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Opc = X86::MOVAPDmr;
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if (Aligned)
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Opc = X86::MOVAPSmr;
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else
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Opc = X86::MOVUPSmr;
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break;
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case MVT::v4i32:
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case MVT::v2i64:
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case MVT::v8i16:
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case MVT::v16i8:
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Opc = X86::MOVDQAmr;
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if (Aligned)
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Opc = X86::MOVDQAmr;
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else
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Opc = X86::MOVDQUmr;
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break;
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}
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addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
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DL, TII.get(Opc)), AM).addReg(Val);
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DL, TII.get(Opc)), AM).addReg(ValReg);
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return true;
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}
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bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val,
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const X86AddressMode &AM) {
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const X86AddressMode &AM, bool Aligned) {
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// Handle 'null' like i32/i64 0.
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if (isa<ConstantPointerNull>(Val))
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Val = Constant::getNullValue(TD.getIntPtrType(Val->getContext()));
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@ -314,7 +326,7 @@ bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val,
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if (ValReg == 0)
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return false;
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return X86FastEmitStore(VT, ValReg, AM);
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return X86FastEmitStore(VT, ValReg, AM, Aligned);
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}
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/// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
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@ -688,6 +700,10 @@ bool X86FastISel::X86SelectStore(const Instruction *I) {
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if (S->isAtomic())
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return false;
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unsigned SABIAlignment =
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TD.getABITypeAlignment(S->getValueOperand()->getType());
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bool Aligned = S->getAlignment() == 0 || S->getAlignment() >= SABIAlignment;
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MVT VT;
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if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true))
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return false;
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@ -696,7 +712,7 @@ bool X86FastISel::X86SelectStore(const Instruction *I) {
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if (!X86SelectAddress(I->getOperand(1), AM))
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return false;
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return X86FastEmitStore(VT, I->getOperand(0), AM);
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return X86FastEmitStore(VT, I->getOperand(0), AM, Aligned);
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}
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/// X86SelectRet - Select and emit code to implement ret instructions.
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@ -20,7 +20,7 @@ entry:
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%2 = load <4 x float>* %p3, align 16
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%3 = load <4 x float>* %p4, align 16
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%4 = load <4 x float>* %p5, align 16
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; CHECK: movaps {{%xmm[0-7]}}, (%esp)
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; CHECK: movups {{%xmm[0-7]}}, (%esp)
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; CHECK-NEXT: calll _dovectortest
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call void @dovectortest(<4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x float> %3, <4 x float> %4)
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ret void
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48
test/CodeGen/X86/fast-isel-store.ll
Normal file
48
test/CodeGen/X86/fast-isel-store.ll
Normal file
@ -0,0 +1,48 @@
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; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort -mattr=+sse2 < %s | FileCheck %s
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; RUN: llc -mtriple=i686-none-linux -fast-isel -fast-isel-abort -mattr=+sse2 < %s | FileCheck %s
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define i32 @test_store_32(i32* nocapture %addr, i32 %value) {
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entry:
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store i32 %value, i32* %addr, align 1
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ret i32 %value
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}
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; CHECK: ret
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define i16 @test_store_16(i16* nocapture %addr, i16 %value) {
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entry:
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store i16 %value, i16* %addr, align 1
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ret i16 %value
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}
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; CHECK: ret
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define <4 x i32> @test_store_4xi32(<4 x i32>* nocapture %addr, <4 x i32> %value, <4 x i32> %value2) {
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; CHECK: movdqu
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; CHECK: ret
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%foo = add <4 x i32> %value, %value2 ; to force integer type on store
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store <4 x i32> %foo, <4 x i32>* %addr, align 1
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ret <4 x i32> %foo
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}
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define <4 x i32> @test_store_4xi32_aligned(<4 x i32>* nocapture %addr, <4 x i32> %value, <4 x i32> %value2) {
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; CHECK: movdqa
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; CHECK: ret
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%foo = add <4 x i32> %value, %value2 ; to force integer type on store
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store <4 x i32> %foo, <4 x i32>* %addr, align 16
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ret <4 x i32> %foo
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}
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define <4 x float> @test_store_4xf32(<4 x float>* nocapture %addr, <4 x float> %value) {
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; CHECK: movups
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; CHECK: ret
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store <4 x float> %value, <4 x float>* %addr, align 1
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ret <4 x float> %value
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}
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define <4 x float> @test_store_4xf32_aligned(<4 x float>* nocapture %addr, <4 x float> %value) {
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; CHECK: movaps
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; CHECK: ret
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store <4 x float> %value, <4 x float>* %addr, align 16
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ret <4 x float> %value
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}
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@ -1,18 +0,0 @@
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; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort < %s | FileCheck %s
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; RUN: llc -mtriple=i686-none-linux -fast-isel -fast-isel-abort < %s | FileCheck %s
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define i32 @test_store_32(i32* nocapture %addr, i32 %value) {
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entry:
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store i32 %value, i32* %addr, align 1
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ret i32 %value
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}
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; CHECK: ret
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define i16 @test_store_16(i16* nocapture %addr, i16 %value) {
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entry:
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store i16 %value, i16* %addr, align 1
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ret i16 %value
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}
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; CHECK: ret
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