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The "excess register pressure" returned by HighRegPressure() is not accurate enough to factor into scheduling priority. Eliminate it and add early exits to speed up scheduling.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109449 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2010-07-26 21:49:07 +00:00
parent 25a6ab0144
commit e0e925efb3
1 changed files with 20 additions and 41 deletions
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61
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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@@ -1191,13 +1191,10 @@ namespace {
SU->NodeQueueId = 0; SU->NodeQueueId = 0;
} }
bool HighRegPressure(const SUnit *SU, unsigned &Excess) const { bool HighRegPressure(const SUnit *SU) const {
Excess = 0;
if (!TLI) if (!TLI)
return false; return false;
bool High = false;
for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end(); for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
I != E; ++I) { I != E; ++I) {
if (I->isCtrl()) if (I->isCtrl())
@@ -1209,10 +1206,8 @@ namespace {
EVT VT = PN->getValueType(0); EVT VT = PN->getValueType(0);
unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
unsigned Cost = TLI->getRepRegClassCostFor(VT); unsigned Cost = TLI->getRepRegClassCostFor(VT);
if ((RegPressure[RCId] + Cost) >= RegLimit[RCId]) { if ((RegPressure[RCId] + Cost) >= RegLimit[RCId])
High = true; return true;
Excess += (RegPressure[RCId] + Cost) - RegLimit[RCId];
}
} }
continue; continue;
} }
@@ -1225,10 +1220,8 @@ namespace {
unsigned Cost = TLI->getRepRegClassCostFor(VT); unsigned Cost = TLI->getRepRegClassCostFor(VT);
// Check if this increases register pressure of the specific register // Check if this increases register pressure of the specific register
// class to the point where it would cause spills. // class to the point where it would cause spills.
if ((RegPressure[RCId] + Cost) >= RegLimit[RCId]) { if ((RegPressure[RCId] + Cost) >= RegLimit[RCId])
High = true; return true;
Excess += (RegPressure[RCId] + Cost) - RegLimit[RCId];
}
continue; continue;
} else if (POpc == TargetOpcode::INSERT_SUBREG || } else if (POpc == TargetOpcode::INSERT_SUBREG ||
POpc == TargetOpcode::SUBREG_TO_REG) { POpc == TargetOpcode::SUBREG_TO_REG) {
@@ -1237,29 +1230,27 @@ namespace {
unsigned Cost = TLI->getRepRegClassCostFor(VT); unsigned Cost = TLI->getRepRegClassCostFor(VT);
// Check if this increases register pressure of the specific register // Check if this increases register pressure of the specific register
// class to the point where it would cause spills. // class to the point where it would cause spills.
if ((RegPressure[RCId] + Cost) >= RegLimit[RCId]) { if ((RegPressure[RCId] + Cost) >= RegLimit[RCId])
High = true; return true;
Excess += (RegPressure[RCId] + Cost) - RegLimit[RCId];
}
continue; continue;
} }
unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs(); unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs();
for (unsigned i = 0; i != NumDefs; ++i) { for (unsigned i = 0; i != NumDefs; ++i) {
EVT VT = PN->getValueType(i); EVT VT = PN->getValueType(i);
unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
if (RegPressure[RCId] >= RegLimit[RCId])
return true; // Reg pressure already high.
unsigned Cost = TLI->getRepRegClassCostFor(VT);
if (!PN->hasAnyUseOfValue(i)) if (!PN->hasAnyUseOfValue(i))
continue; continue;
unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
unsigned Cost = TLI->getRepRegClassCostFor(VT);
// Check if this increases register pressure of the specific register // Check if this increases register pressure of the specific register
// class to the point where it would cause spills. // class to the point where it would cause spills.
if ((RegPressure[RCId] + Cost) >= RegLimit[RCId]) { if ((RegPressure[RCId] + Cost) >= RegLimit[RCId])
High = true; return true;
Excess += (RegPressure[RCId] + Cost) - RegLimit[RCId];
}
} }
} }
return High; return false;
} }
void ScheduledNode(SUnit *SU) { void ScheduledNode(SUnit *SU) {
@@ -1558,21 +1549,15 @@ bool src_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
} }
bool hybrid_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const{ bool hybrid_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const{
unsigned LExcess, RExcess; bool LHigh = SPQ->HighRegPressure(left);
bool LHigh = SPQ->HighRegPressure(left, LExcess); bool RHigh = SPQ->HighRegPressure(right);
bool RHigh = SPQ->HighRegPressure(right, RExcess);
// Avoid causing spills. If register pressure is high, schedule for // Avoid causing spills. If register pressure is high, schedule for
// register pressure reduction. // register pressure reduction.
if (LHigh && !RHigh) if (LHigh && !RHigh)
return true; return true;
else if (!LHigh && RHigh) else if (!LHigh && RHigh)
return false; return false;
else if (LHigh && RHigh) { else if (!LHigh && !RHigh) {
if (LExcess > RExcess)
return true;
else if (LExcess < RExcess)
return false;
} else {
// Low register pressure situation, schedule for latency if possible. // Low register pressure situation, schedule for latency if possible.
bool LStall = left->SchedulingPref == Sched::Latency && bool LStall = left->SchedulingPref == Sched::Latency &&
SPQ->getCurCycle() < left->getHeight(); SPQ->getCurCycle() < left->getHeight();
@@ -1606,21 +1591,15 @@ bool hybrid_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const{
bool ilp_ls_rr_sort::operator()(const SUnit *left, bool ilp_ls_rr_sort::operator()(const SUnit *left,
const SUnit *right) const { const SUnit *right) const {
unsigned LExcess, RExcess; bool LHigh = SPQ->HighRegPressure(left);
bool LHigh = SPQ->HighRegPressure(left, LExcess); bool RHigh = SPQ->HighRegPressure(right);
bool RHigh = SPQ->HighRegPressure(right, RExcess);
// Avoid causing spills. If register pressure is high, schedule for // Avoid causing spills. If register pressure is high, schedule for
// register pressure reduction. // register pressure reduction.
if (LHigh && !RHigh) if (LHigh && !RHigh)
return true; return true;
else if (!LHigh && RHigh) else if (!LHigh && RHigh)
return false; return false;
else if (LHigh && RHigh) { else if (!LHigh && !RHigh) {
if (LExcess > RExcess)
return true;
else if (LExcess < RExcess)
return false;
} else {
// Low register pressure situation, schedule to maximize instruction level // Low register pressure situation, schedule to maximize instruction level
// parallelism. // parallelism.
if (left->NumPreds > right->NumPreds) if (left->NumPreds > right->NumPreds)