6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-08 19:25:47 +00:00
Code Issues Projects Releases Wiki Activity

Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118600 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2010-11-09 18:43:54 +00:00
parent 80f3d786ad
commit e0ee08e367
1 changed files with 2 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/ARM/ARMInstrInfo.td
View File

@@ -851,6 +851,7 @@ multiclass AI_ldr1<bit opc22, string opc, InstrItinClass iii,
bits<17> shift; bits<17> shift;
let Inst{23} = shift{12}; // U (add = ('U' == 1)) let Inst{23} = shift{12}; // U (add = ('U' == 1))
let Inst{19-16} = shift{16-13}; // Rn let Inst{19-16} = shift{16-13}; // Rn
let Inst{15-12} = Rt;
let Inst{11-0} = shift{11-0}; let Inst{11-0} = shift{11-0};
} }
} }
@@ -879,6 +880,7 @@ multiclass AI_str1<bit opc22, string opc, InstrItinClass iii,
bits<17> shift; bits<17> shift;
let Inst{23} = shift{12}; // U (add = ('U' == 1)) let Inst{23} = shift{12}; // U (add = ('U' == 1))
let Inst{19-16} = shift{16-13}; // Rn let Inst{19-16} = shift{16-13}; // Rn
let Inst{15-12} = Rt;
let Inst{11-0} = shift{11-0}; let Inst{11-0} = shift{11-0};
} }
} }