6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-24 08:33:39 +00:00
Code Issues Projects Releases Wiki Activity

Use sublw for comparison with literals instead of subwf.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63382 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjiv Gupta 2009-01-30 07:55:25 +00:00
parent 7ad9b51278
commit e0ffc92508
1 changed files with 10 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
lib/Target/PIC16/PIC16ISelLowering.cpp
View File

@ -1288,7 +1288,6 @@ SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS,
} }
PIC16CC = DAG.getConstant(CondCode, MVT::i8); PIC16CC = DAG.getConstant(CondCode, MVT::i8);
SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag);
// These are signed comparisons. // These are signed comparisons.
SDValue Mask = DAG.getConstant(128, MVT::i8); SDValue Mask = DAG.getConstant(128, MVT::i8);
@ -1296,15 +1295,18 @@ SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS,
LHS = DAG.getNode (ISD::XOR, MVT::i8, LHS, Mask); LHS = DAG.getNode (ISD::XOR, MVT::i8, LHS, Mask);
RHS = DAG.getNode (ISD::XOR, MVT::i8, RHS, Mask); RHS = DAG.getNode (ISD::XOR, MVT::i8, RHS, Mask);
} }
SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag);
// We can use a subtract operation to set the condition codes. But // We can use a subtract operation to set the condition codes. But
// we need to put one operand in memory if required. // we need to put one operand in memory if required.
// Nothing to do if the first operand is already a direct load and it has // Nothing to do if the first operand is already a valid type (direct load
// only one use. // for subwf and literal for sublw) and it is used by this operation only.
if (! (isDirectLoad(LHS) && LHS.hasOneUse())) if ((LHS.getOpcode() == ISD::Constant || isDirectLoad(LHS))
// Put first operand on stack. && LHS.hasOneUse())
LHS = ConvertToMemOperand (LHS, DAG); return DAG.getNode(PIC16ISD::SUBCC, VTs, LHS, RHS);
SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag); // else convert the first operand to mem.
LHS = ConvertToMemOperand (LHS, DAG);
return DAG.getNode(PIC16ISD::SUBCC, VTs, LHS, RHS); return DAG.getNode(PIC16ISD::SUBCC, VTs, LHS, RHS);
} }