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Make XOP imply AVX as its needed to legalize the registers types.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155891 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-05-01 05:41:41 +00:00
parent c49c6e154a
commit e106d2e2ac
1 changed files with 2 additions and 1 deletions
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lib/Target/X86/X86.td
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@ -96,7 +96,8 @@ def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
"Enable four-operand fused multiple-add", "Enable four-operand fused multiple-add",
[FeatureAVX]>; [FeatureAVX]>;
def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true", def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
"Enable XOP instructions">; "Enable XOP instructions",
[FeatureAVX]>;
def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem", def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
"HasVectorUAMem", "true", "HasVectorUAMem", "true",
"Allow unaligned memory operands on vector/SIMD instructions">; "Allow unaligned memory operands on vector/SIMD instructions">;