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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-21 09:40:22 +00:00
Fix call setup for PIC.
Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160774 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -46,6 +46,15 @@ class FEXT_RI16_ins<bits<5> _op, string asmstr,
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class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
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FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
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class FEXT_2RI16_ins<bits<5> _op, string asmstr,
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InstrItinClass itin>:
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FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
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!strconcat(asmstr, "\t$rx, $imm"), [], itin> {
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let Constraints = "$rx_ = $rx";
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}
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//
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// RR-type instruction format
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//
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@ -80,6 +89,20 @@ def mem16 : Operand<i32> {
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}
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//
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// Format: ADDIU rx, immediate MIPS16e
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// Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
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// To add a constant to a 32-bit integer.
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//
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class AddiuRxImmX16_base: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
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def AddiuRxImmX16: AddiuRxImmX16_base;
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class AddiuRxRxImmX16_base: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>;
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def AddiuRxRxImmX16: AddiuRxRxImmX16_base;
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//
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// Format: ADDIU rx, pc, immediate MIPS16e
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// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
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// To add a constant to the program counter.
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@ -240,4 +263,7 @@ def ADJCALLSTACKUP16 : MipsPseudo16<(outs), (ins uimm16:$amt1, uimm16:$amt2),
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// Small immediates
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def : Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
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def : Mips16Pat<(MipsLo tglobaladdr:$in), (LiRxImmX16 tglobaladdr:$in)>;
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def : Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
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(AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
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@ -2645,7 +2645,6 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
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SDValue InChain = CLI.Chain;
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SDValue Callee = CLI.Callee;
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SDValue CalleeSave = CLI.Callee;
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bool &isTailCall = CLI.IsTailCall;
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CallingConv::ID CallConv = CLI.CallConv;
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bool isVarArg = CLI.IsVarArg;
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@ -2867,6 +2866,9 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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}
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}
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// T9 register operand.
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SDValue T9;
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// T9 should contain the address of the callee function if
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// -reloction-model=pic or it is an indirect call.
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if (IsPICCall || !GlobalOrExternal) {
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@ -2874,7 +2876,11 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
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Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0));
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InFlag = Chain.getValue(1);
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Callee = DAG.getRegister(T9Reg, getPointerTy());
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if (Subtarget->inMips16Mode())
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T9 = DAG.getRegister(T9Reg, getPointerTy());
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else
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Callee = DAG.getRegister(T9Reg, getPointerTy());
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}
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// Insert node "GP copy globalreg" before call to function.
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@ -2902,7 +2908,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
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SmallVector<SDValue, 8> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Subtarget->inMips16Mode()? CalleeSave: Callee);
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Ops.push_back(Callee);
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// Add argument registers to the end of the list so that they are
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// known live into the call.
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@ -2910,8 +2916,10 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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Ops.push_back(DAG.getRegister(RegsToPass[i].first,
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RegsToPass[i].second.getValueType()));
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if (Subtarget->inMips16Mode())
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Ops.push_back(Callee);
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// Add T9 register operand.
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if (T9.getNode())
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Ops.push_back(T9);
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// Add a register mask operand representing the call-preserved registers.
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const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
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const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
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32
test/CodeGen/Mips/helloworld.ll
Normal file
32
test/CodeGen/Mips/helloworld.ll
Normal file
@ -0,0 +1,32 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=C1
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=C2
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=PE
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=SR
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@.str = private unnamed_addr constant [13 x i8] c"hello world\0A\00", align 1
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define i32 @main() nounwind {
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entry:
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%call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0))
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ret i32 0
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; SR: .set mips16 # @main
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; SR: save $ra, [[FS:[0-9]+]]
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; PE: li $[[T1:[0-9]+]], %hi(_gp_disp)
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; PE: addiu $[[T2:[0-9]+]], $pc, %lo(_gp_disp)
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; PE: sll $[[T3:[0-9]+]], $[[T1]], 16
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; C1: lw ${{[0-9]+}}, %got($.str)(${{[0-9]+}})
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; C2: lw ${{[0-9]+}}, %call16(printf)(${{[0-9]+}})
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; C1: addiu ${{[0-9]+}}, %lo($.str)
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; C2: move $25, ${{[0-9]+}}
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; C1: move $gp, ${{[0-9]+}}
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; C1: jalr ${{[0-9]+}}
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; SR: restore $ra, [[FS]]
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; PE: li $2, 0
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; PE: jr $ra
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}
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declare i32 @printf(i8*, ...)
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@ -1,17 +0,0 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@.str = private unnamed_addr constant [13 x i8] c"hello world\0A\00", align 1
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define i32 @main() nounwind {
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entry:
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%call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0))
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ret i32 0
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; 16: .set mips16 # @main
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; 16: move $gp, ${{[0-9]+}}
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; 16: jalr ${{[0-9]+}}
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; 16: li $2, 0
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}
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declare i32 @printf(i8*, ...)
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@ -1,18 +0,0 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@.str = private unnamed_addr constant [13 x i8] c"hello world\0A\00", align 1
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define i32 @main() nounwind {
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entry:
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%call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0))
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ret i32 0
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; 16: .set mips16 # @main
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; 16: li $[[T1:[0-9]+]], %hi(_gp_disp)
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; 16: addiu $[[T2:[0-9]+]], $pc, %lo(_gp_disp)
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; 16: sll $[[T3:[0-9]+]], $[[T1]], 16
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; 16: li $2, 0
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}
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declare i32 @printf(i8*, ...)
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@ -1,16 +0,0 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@.str = private unnamed_addr constant [13 x i8] c"hello world\0A\00", align 1
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define i32 @main() nounwind {
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entry:
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%call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0))
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ret i32 0
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; 16: .set mips16 # @main
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; 16: save $ra, [[FS:[0-9]+]]
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; 16: restore $ra, [[FS]]
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}
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declare i32 @printf(i8*, ...)
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