From e12bf1875481b02d07b6ce9c153ec3410068e234 Mon Sep 17 00:00:00 2001 From: Nadav Rotem Date: Fri, 4 Jan 2013 17:35:21 +0000 Subject: [PATCH] Revert revision: 171467. This transformation is incorrect and makes some tests fail. Original message: Simplified TRUNCATE operation that comes after SETCC. It is possible since SETCC result is 0 or -1. Added a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171468 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 23 +++-------------------- test/CodeGen/X86/avx-trunc.ll | 15 --------------- 2 files changed, 3 insertions(+), 35 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 9a553d61bfb..eca63f80ae0 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -14661,29 +14661,12 @@ static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); } -/// PerformTruncateCombine - In some cases a sequence with "truncate" -/// operation may be simplified. +/// PerformTruncateCombine - Converts truncate operation to +/// a sequence of vector shuffle operations. +/// It is possible when we truncate 256-bit vector to 128-bit vector static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) { - EVT VT = N->getValueType(0); - if (DCI.isBeforeLegalize() || !VT.isVector()) - return SDValue(); - - SDValue In = N->getOperand(0); - // Optimize the sequence setcc -> truncate - if (In.getOpcode() == ISD::SETCC) { - DebugLoc DL = N->getDebugLoc(); - EVT InVT = In.getValueType(); - - // The vector element is all ones or all zero. Just take a half of it. - EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(), - InVT.getVectorNumElements()/2); - SDValue HalfVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, In, - DAG.getIntPtrConstant(0)); - assert(HalfVT.getSizeInBits() == VT.getSizeInBits()); - return DAG.getNode(ISD::BITCAST, DL, VT, HalfVec); - } return SDValue(); } diff --git a/test/CodeGen/X86/avx-trunc.ll b/test/CodeGen/X86/avx-trunc.ll index aa186a05f21..d0077366444 100755 --- a/test/CodeGen/X86/avx-trunc.ll +++ b/test/CodeGen/X86/avx-trunc.ll @@ -13,18 +13,3 @@ define <8 x i16> @trunc_32_16(<8 x i32> %A) nounwind uwtable readnone ssp{ ret <8 x i16>%B } -define <8 x i16> @trunc_after_setcc(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x float> %d) { -; CHECK: trunc_after_setcc -; CHECK: vcmpltps -; CHECK-NOT: vextract -; CHECK: vcmpltps -; CHECK-NEXT: vandps -; CHECK-NEXT: vandps -; CHECK: ret - %res1 = fcmp olt <8 x float> %a, %b - %res2 = fcmp olt <8 x float> %c, %d - %andr = and <8 x i1>%res1, %res2 - %ex = zext <8 x i1> %andr to <8 x i16> - ret <8 x i16>%ex -} -