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Teach the addressing mode stuff to fold "%lo" into 'ri' addressing modes,

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allowing us to compile this:

to this:

%G1 = external global int
%G2 = external global int
void %test() {
        %X = load int* %G1
        store int %X, int* %G2
        ret void
}

test:
        save -96, %sp, %sp
        sethi %hi(G1), %l0
        ld [%l0+%lo(G1)], %l0
        sethi %hi(G2), %l1
        st %l0, [%l1+%lo(G2)]
        restore %g0, %g0, %g0
        retl
        nop

instead of this:

test:
        save -96, %sp, %sp
        sethi %hi(G1), %l0
        or %g0, %lo(G1), %l1
        ld [%l1+%l0], %l0
        sethi %hi(G2), %l1
        or %g0, %lo(G2), %l2
        st %l0, [%l2+%l1]
        restore %g0, %g0, %g0
        retl
        nop


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24812 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2005-12-18 02:27:00 +00:00
parent e357246c6b
commit e1389ad43a
4 changed files with 40 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/Sparc/SparcAsmPrinter.cpp
View File

@@ -186,7 +186,13 @@ void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
void SparcV8AsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) {
printOperand(MI, opNum);
O << "+";
printOperand(MI, opNum+1);
if (MI->getOperand(opNum+1).getType() == MachineOperand::MO_GlobalAddress) {
O << "%lo(";
printOperand(MI, opNum+1);
O << ")";
} else {
printOperand(MI, opNum+1);
}
}

13
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@@ -309,6 +309,9 @@ bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
Predicate_simm13(Addr.getOperand(1).Val))
return false; // Let the reg+imm pattern catch this!
if (Addr.getOperand(0).getOpcode() == V8ISD::Lo ||
Addr.getOperand(1).getOpcode() == V8ISD::Lo)
return false; // Let the reg+imm pattern catch this!
R1 = Select(Addr.getOperand(0));
R2 = Select(Addr.getOperand(1));
return true;
@@ -328,6 +331,16 @@ bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
return true;
}
if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
Base = Select(Addr.getOperand(1));
Offset = Addr.getOperand(0).getOperand(0);
return true;
}
if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
Base = Select(Addr.getOperand(0));
Offset = Addr.getOperand(1).getOperand(0);
return true;
}
}
Base = Select(Addr);
Offset = CurDAG->getTargetConstant(0, MVT::i32);

8
lib/Target/SparcV8/SparcV8AsmPrinter.cpp
View File

@@ -186,7 +186,13 @@ void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
void SparcV8AsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) {
printOperand(MI, opNum);
O << "+";
printOperand(MI, opNum+1);
if (MI->getOperand(opNum+1).getType() == MachineOperand::MO_GlobalAddress) {
O << "%lo(";
printOperand(MI, opNum+1);
O << ")";
} else {
printOperand(MI, opNum+1);
}
}

13
lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
View File

@@ -309,6 +309,9 @@ bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
Predicate_simm13(Addr.getOperand(1).Val))
return false; // Let the reg+imm pattern catch this!
if (Addr.getOperand(0).getOpcode() == V8ISD::Lo ||
Addr.getOperand(1).getOpcode() == V8ISD::Lo)
return false; // Let the reg+imm pattern catch this!
R1 = Select(Addr.getOperand(0));
R2 = Select(Addr.getOperand(1));
return true;
@@ -328,6 +331,16 @@ bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
return true;
}
if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
Base = Select(Addr.getOperand(1));
Offset = Addr.getOperand(0).getOperand(0);
return true;
}
if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
Base = Select(Addr.getOperand(0));
Offset = Addr.getOperand(1).getOperand(0);
return true;
}
}
Base = Select(Addr);
Offset = CurDAG->getTargetConstant(0, MVT::i32);