From e152eac63efa836cbb109d79e4307516fa16f1a6 Mon Sep 17 00:00:00 2001 From: Ulrich Weigand Date: Fri, 17 May 2013 12:37:21 +0000 Subject: [PATCH] [PowerPC] Merge/rename PPC fixup types Now that fixup_ppc_ha16 and fixup_ppc_lo16 are being treated exactly the same everywhere, it no longer makes sense to have two fixup types. This patch merges them both into a single type fixup_ppc_half16, and renames fixup_ppc_lo16_ds to fixup_ppc_half16ds for consistency. (The half16 and half16ds names are taken from the description of relocation types in the PowerPC ABI.) No change in code generation expected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182092 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../PowerPC/MCTargetDesc/PPCAsmBackend.cpp | 18 +++---- .../MCTargetDesc/PPCELFObjectWriter.cpp | 5 +- .../PowerPC/MCTargetDesc/PPCFixupKinds.h | 14 ++---- .../PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp | 8 +-- test/MC/PowerPC/ppc64-fixups.s | 50 +++++++++---------- 5 files changed, 42 insertions(+), 53 deletions(-) diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp index 9ec5f0e0b54..3fa2e0933cf 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp @@ -37,13 +37,9 @@ static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) { return Value & 0xfffc; case PPC::fixup_ppc_br24: return Value & 0x3fffffc; -#if 0 - case PPC::fixup_ppc_hi16: -#endif - case PPC::fixup_ppc_ha16: - case PPC::fixup_ppc_lo16: + case PPC::fixup_ppc_half16: return Value & 0xffff; - case PPC::fixup_ppc_lo16_ds: + case PPC::fixup_ppc_half16ds: return Value & 0xfffc; } } @@ -55,9 +51,8 @@ static unsigned getFixupKindNumBytes(unsigned Kind) { case FK_Data_1: return 1; case FK_Data_2: - case PPC::fixup_ppc_ha16: - case PPC::fixup_ppc_lo16: - case PPC::fixup_ppc_lo16_ds: + case PPC::fixup_ppc_half16: + case PPC::fixup_ppc_half16ds: return 2; case FK_Data_4: case PPC::fixup_ppc_brcond14: @@ -98,9 +93,8 @@ public: // name offset bits flags { "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_ppc_lo16", 0, 16, 0 }, - { "fixup_ppc_ha16", 0, 16, 0 }, - { "fixup_ppc_lo16_ds", 0, 14, 0 }, + { "fixup_ppc_half16", 0, 16, 0 }, + { "fixup_ppc_half16ds", 0, 14, 0 }, { "fixup_ppc_tlsreg", 0, 0, 0 }, { "fixup_ppc_nofixup", 0, 0, 0 } }; diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp index 5193dca2882..5c272c0ee97 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp @@ -81,8 +81,7 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const MCValue &Target, case PPC::fixup_ppc_brcond14: Type = ELF::R_PPC_ADDR14; // XXX: or BRNTAKEN?_ break; - case PPC::fixup_ppc_ha16: - case PPC::fixup_ppc_lo16: + case PPC::fixup_ppc_half16: switch (Modifier) { default: llvm_unreachable("Unsupported Modifier"); case MCSymbolRefExpr::VK_PPC_TPREL16_HA: @@ -134,7 +133,7 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const MCValue &Target, break; } break; - case PPC::fixup_ppc_lo16_ds: + case PPC::fixup_ppc_half16ds: switch (Modifier) { default: llvm_unreachable("Unsupported Modifier"); case MCSymbolRefExpr::VK_None: diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h b/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h index 86c44f57a5e..3ea59f0b2fc 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h +++ b/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h @@ -25,17 +25,13 @@ enum Fixups { /// branches. fixup_ppc_brcond14, - /// fixup_ppc_lo16 - A 16-bit fixup corresponding to lo16(_foo) for instrs - /// like 'li'. - fixup_ppc_lo16, + /// fixup_ppc_half16 - A 16-bit fixup corresponding to lo16(_foo) + /// or ha16(_foo) for instrs like 'li' or 'addis'. + fixup_ppc_half16, - /// fixup_ppc_ha16 - A 16-bit fixup corresponding to ha16(_foo) for instrs - /// like 'lis'. - fixup_ppc_ha16, - - /// fixup_ppc_lo16_ds - A 14-bit fixup corresponding to lo16(_foo) with + /// fixup_ppc_half16ds - A 14-bit fixup corresponding to lo16(_foo) with /// implied 2 zero bits for instrs like 'std'. - fixup_ppc_lo16_ds, + fixup_ppc_half16ds, /// fixup_ppc_tlsreg - Insert thread-pointer register number. fixup_ppc_tlsreg, diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp index 244c534d9c9..34bd483ee0f 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -143,7 +143,7 @@ unsigned PPCMCCodeEmitter::getHA16Encoding(const MCInst &MI, unsigned OpNo, // Add a fixup for the branch target. Fixups.push_back(MCFixup::Create(2, MO.getExpr(), - (MCFixupKind)PPC::fixup_ppc_ha16)); + (MCFixupKind)PPC::fixup_ppc_half16)); return 0; } @@ -154,7 +154,7 @@ unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo, // Add a fixup for the branch target. Fixups.push_back(MCFixup::Create(2, MO.getExpr(), - (MCFixupKind)PPC::fixup_ppc_lo16)); + (MCFixupKind)PPC::fixup_ppc_half16)); return 0; } @@ -171,7 +171,7 @@ unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo, // Add a fixup for the displacement field. Fixups.push_back(MCFixup::Create(2, MO.getExpr(), - (MCFixupKind)PPC::fixup_ppc_lo16)); + (MCFixupKind)PPC::fixup_ppc_half16)); return RegBits; } @@ -189,7 +189,7 @@ unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo, // Add a fixup for the displacement field. Fixups.push_back(MCFixup::Create(2, MO.getExpr(), - (MCFixupKind)PPC::fixup_ppc_lo16_ds)); + (MCFixupKind)PPC::fixup_ppc_half16ds)); return RegBits; } diff --git a/test/MC/PowerPC/ppc64-fixups.s b/test/MC/PowerPC/ppc64-fixups.s index 25c1736f101..38937c80146 100644 --- a/test/MC/PowerPC/ppc64-fixups.s +++ b/test/MC/PowerPC/ppc64-fixups.s @@ -8,77 +8,77 @@ # FIXME: .TOC.@tocbase # CHECK: li 3, target@l # encoding: [0x38,0x60,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16 +# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0 li 3, target@l # CHECK: addis 3, 3, target@ha # encoding: [0x3c,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_ha16 +# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0 addis 3, 3, target@ha # CHECK: lis 3, target@ha # encoding: [0x3c,0x60,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_ha16 +# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0 lis 3, target@ha # CHECK: addi 4, 3, target@l # encoding: [0x38,0x83,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16 +# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0 addi 4, 3, target@l # CHECK: li 3, target@ha # encoding: [0x38,0x60,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_lo16 +# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0 li 3, target@ha # CHECK: lis 3, target@l # encoding: [0x3c,0x60,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_ha16 +# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0 lis 3, target@l # CHECK: li 3, target # encoding: [0x38,0x60,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target, kind: fixup_ppc_lo16 +# CHECK-NEXT: # fixup A - offset: 2, value: target, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16 target 0x0 li 3, target # CHECK: lis 3, target # encoding: [0x3c,0x60,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target, kind: fixup_ppc_ha16 +# CHECK-NEXT: # fixup A - offset: 2, value: target, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16 target 0x0 lis 3, target # CHECK: lwz 1, target@l(3) # encoding: [0x80,0x23,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16 +# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0 lwz 1, target@l(3) # CHECK: ld 1, target@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16_ds +# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16ds # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO_DS target 0x0 ld 1, target@l(3) # CHECK: ld 1, target@toc(2) # encoding: [0xe8,0x22,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 2, value: target@toc, kind: fixup_ppc_lo16_ds +# CHECK-NEXT: # fixup A - offset: 2, value: target@toc, kind: fixup_ppc_half16ds # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_DS target 0x0 ld 1, target@toc(2) # CHECK: addis 3, 2, target@toc@ha # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@ha, kind: fixup_ppc_ha16 +# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@ha, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_HA target 0x0 addis 3, 2, target@toc@ha # CHECK: addi 4, 3, target@toc@l # encoding: [0x38,0x83,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_lo16 +# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0 addi 4, 3, target@toc@l # CHECK: lwz 1, target@toc@l(3) # encoding: [0x80,0x23,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_lo16 +# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0 lwz 1, target@toc@l(3) # CHECK: ld 1, target@toc@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_lo16_ds +# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_half16ds # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO_DS target 0x0 ld 1, target@toc@l(3) @@ -86,55 +86,55 @@ # CHECK: addis 3, 2, target@tprel@ha # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@ha, kind: fixup_ppc_ha16 +# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@ha, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HA target 0x0 addis 3, 2, target@tprel@ha # CHECK: addi 3, 3, target@tprel@l # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@l, kind: fixup_ppc_lo16 +# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@l, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_LO target 0x0 addi 3, 3, target@tprel@l # CHECK: addis 3, 2, target@dtprel@ha # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@ha, kind: fixup_ppc_ha16 +# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@ha, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HA target 0x0 addis 3, 2, target@dtprel@ha # CHECK: addi 3, 3, target@dtprel@l # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@l, kind: fixup_ppc_lo16 +# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@l, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_LO target 0x0 addi 3, 3, target@dtprel@l # CHECK: addis 3, 2, target@got@tprel@ha # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@ha, kind: fixup_ppc_ha16 +# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@ha, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_HA target 0x0 addis 3, 2, target@got@tprel@ha # CHECK: ld 1, target@got@tprel@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@l, kind: fixup_ppc_lo16_ds +# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@l, kind: fixup_ppc_half16ds # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_LO_DS target 0x0 ld 1, target@got@tprel@l(3) # CHECK: addis 3, 2, target@got@tlsgd@ha # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@ha, kind: fixup_ppc_ha16 +# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@ha, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_HA target 0x0 addis 3, 2, target@got@tlsgd@ha # CHECK: addi 3, 3, target@got@tlsgd@l # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@l, kind: fixup_ppc_lo16 +# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@l, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_LO target 0x0 addi 3, 3, target@got@tlsgd@l # CHECK: addis 3, 2, target@got@tlsld@ha # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@ha, kind: fixup_ppc_ha16 +# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@ha, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_HA target 0x0 addis 3, 2, target@got@tlsld@ha # CHECK: addi 3, 3, target@got@tlsld@l # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@l, kind: fixup_ppc_lo16 +# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@l, kind: fixup_ppc_half16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_LO target 0x0 addi 3, 3, target@got@tlsld@l