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[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. MSP430 edition

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207507 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
2014-04-29 07:58:09 +00:00
parent 91b10fb0e9
commit e17a0260a8
11 changed files with 84 additions and 83 deletions
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2
lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h
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@@ -25,7 +25,7 @@ namespace llvm {
const MCRegisterInfo &MRI) const MCRegisterInfo &MRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MRI) {}
virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot); void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
// Autogenerated by tblgen. // Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O); void printInstruction(const MCInst *MI, raw_ostream &O);

2
lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h
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@@ -20,7 +20,7 @@ namespace llvm {
class StringRef; class StringRef;
class MSP430MCAsmInfo : public MCAsmInfoELF { class MSP430MCAsmInfo : public MCAsmInfoELF {
virtual void anchor(); void anchor() override;
public: public:
explicit MSP430MCAsmInfo(StringRef TT); explicit MSP430MCAsmInfo(StringRef TT);
}; };

8
lib/Target/MSP430/MSP430AsmPrinter.cpp
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@@ -42,7 +42,7 @@ namespace {
MSP430AsmPrinter(TargetMachine &TM, MCStreamer &Streamer) MSP430AsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
: AsmPrinter(TM, Streamer) {} : AsmPrinter(TM, Streamer) {}
virtual const char *getPassName() const { const char *getPassName() const override {
return "MSP430 Assembly Printer"; return "MSP430 Assembly Printer";
} }
@@ -52,11 +52,11 @@ namespace {
raw_ostream &O); raw_ostream &O);
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant, const char *ExtraCode, unsigned AsmVariant, const char *ExtraCode,
raw_ostream &O); raw_ostream &O) override;
bool PrintAsmMemoryOperand(const MachineInstr *MI, bool PrintAsmMemoryOperand(const MachineInstr *MI,
unsigned OpNo, unsigned AsmVariant, unsigned OpNo, unsigned AsmVariant,
const char *ExtraCode, raw_ostream &O); const char *ExtraCode, raw_ostream &O) override;
void EmitInstruction(const MachineInstr *MI); void EmitInstruction(const MachineInstr *MI) override;
}; };
} // end of anonymous namespace } // end of anonymous namespace

4
lib/Target/MSP430/MSP430BranchSelector.cpp
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@@ -36,9 +36,9 @@ namespace {
/// BlockSizes - The sizes of the basic blocks in the function. /// BlockSizes - The sizes of the basic blocks in the function.
std::vector<unsigned> BlockSizes; std::vector<unsigned> BlockSizes;
virtual bool runOnMachineFunction(MachineFunction &Fn); bool runOnMachineFunction(MachineFunction &Fn) override;
virtual const char *getPassName() const { const char *getPassName() const override {
return "MSP430 Branch Selector"; return "MSP430 Branch Selector";
} }
}; };

22
lib/Target/MSP430/MSP430FrameLowering.h
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@@ -32,26 +32,26 @@ public:
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function. /// the function.
void emitPrologue(MachineFunction &MF) const; void emitPrologue(MachineFunction &MF) const override;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
void eliminateCallFramePseudoInstr(MachineFunction &MF, void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const; MachineBasicBlock::iterator I) const override;
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI, const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const; const TargetRegisterInfo *TRI) const override;
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI, const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const; const TargetRegisterInfo *TRI) const override;
bool hasFP(const MachineFunction &MF) const; bool hasFP(const MachineFunction &MF) const override;
bool hasReservedCallFrame(const MachineFunction &MF) const; bool hasReservedCallFrame(const MachineFunction &MF) const override;
void processFunctionBeforeFrameFinalized(MachineFunction &MF, void processFunctionBeforeFrameFinalized(MachineFunction &MF,
RegScavenger *RS = nullptr) const; RegScavenger *RS = nullptr) const override;
}; };
} // End llvm namespace } // End llvm namespace

9
lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
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@@ -101,7 +101,7 @@ namespace {
Lowering(*TM.getTargetLowering()), Lowering(*TM.getTargetLowering()),
Subtarget(*TM.getSubtargetImpl()) { } Subtarget(*TM.getSubtargetImpl()) { }
virtual const char *getPassName() const { const char *getPassName() const override {
return "MSP430 DAG->DAG Pattern Instruction Selection"; return "MSP430 DAG->DAG Pattern Instruction Selection";
} }
@@ -109,15 +109,14 @@ namespace {
bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM); bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM); bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
virtual bool bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps) override;
std::vector<SDValue> &OutOps);
// Include the pieces autogenerated from the target description. // Include the pieces autogenerated from the target description.
#include "MSP430GenDAGISel.inc" #include "MSP430GenDAGISel.inc"
private: private:
SDNode *Select(SDNode *N); SDNode *Select(SDNode *N) override;
SDNode *SelectIndexedLoad(SDNode *Op); SDNode *SelectIndexedLoad(SDNode *Op);
SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
unsigned Opc8, unsigned Opc16); unsigned Opc8, unsigned Opc16);

52
lib/Target/MSP430/MSP430ISelLowering.h
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@@ -73,14 +73,14 @@ namespace llvm {
public: public:
explicit MSP430TargetLowering(MSP430TargetMachine &TM); explicit MSP430TargetLowering(MSP430TargetMachine &TM);
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i8; } MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i8; }
/// LowerOperation - Provide custom lowering hooks for some operations. /// LowerOperation - Provide custom lowering hooks for some operations.
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
/// getTargetNodeName - This method returns the name of a target specific /// getTargetNodeName - This method returns the name of a target specific
/// DAG node. /// DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const; const char *getTargetNodeName(unsigned Opcode) const override;
SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const; SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
@@ -97,15 +97,16 @@ namespace llvm {
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
TargetLowering::ConstraintType TargetLowering::ConstraintType
getConstraintType(const std::string &Constraint) const; getConstraintType(const std::string &Constraint) const override;
std::pair<unsigned, const TargetRegisterClass*> std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const; getRegForInlineAsmConstraint(const std::string &Constraint,
MVT VT) const override;
/// isTruncateFree - Return true if it's free to truncate a value of type /// isTruncateFree - Return true if it's free to truncate a value of type
/// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in /// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in
/// register R15W to i8 by referencing its sub-register R15B. /// register R15W to i8 by referencing its sub-register R15B.
virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const; bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
virtual bool isTruncateFree(EVT VT1, EVT VT2) const; bool isTruncateFree(EVT VT1, EVT VT2) const override;
/// isZExtFree - Return true if any actual instruction that defines a value /// isZExtFree - Return true if any actual instruction that defines a value
/// of type Ty1 implicit zero-extends the value to Ty2 in the result /// of type Ty1 implicit zero-extends the value to Ty2 in the result
@@ -115,12 +116,12 @@ namespace llvm {
/// necessarily apply to truncate instructions. e.g. on msp430, all /// necessarily apply to truncate instructions. e.g. on msp430, all
/// instructions that define 8-bit values implicit zero-extend the result /// instructions that define 8-bit values implicit zero-extend the result
/// out to 16 bits. /// out to 16 bits.
virtual bool isZExtFree(Type *Ty1, Type *Ty2) const; bool isZExtFree(Type *Ty1, Type *Ty2) const override;
virtual bool isZExtFree(EVT VT1, EVT VT2) const; bool isZExtFree(EVT VT1, EVT VT2) const override;
virtual bool isZExtFree(SDValue Val, EVT VT2) const; bool isZExtFree(SDValue Val, EVT VT2) const override;
MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *BB) const; MachineBasicBlock *BB) const override;
MachineBasicBlock* EmitShiftInstr(MachineInstr *MI, MachineBasicBlock* EmitShiftInstr(MachineInstr *MI,
MachineBasicBlock *BB) const; MachineBasicBlock *BB) const;
@@ -148,28 +149,27 @@ namespace llvm {
SDLoc dl, SelectionDAG &DAG, SDLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const; SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue SDValue
LowerFormalArguments(SDValue Chain, LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
SDLoc dl, SelectionDAG &DAG, SDLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const; SmallVectorImpl<SDValue> &InVals) const override;
virtual SDValue SDValue
LowerCall(TargetLowering::CallLoweringInfo &CLI, LowerCall(TargetLowering::CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const; SmallVectorImpl<SDValue> &InVals) const override;
virtual SDValue SDValue LowerReturn(SDValue Chain,
LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const override;
SDLoc dl, SelectionDAG &DAG) const;
virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
SDValue &Base, SDValue &Base,
SDValue &Offset, SDValue &Offset,
ISD::MemIndexedMode &AM, ISD::MemIndexedMode &AM,
SelectionDAG &DAG) const; SelectionDAG &DAG) const override;
const MSP430Subtarget &Subtarget; const MSP430Subtarget &Subtarget;
const DataLayout *TD; const DataLayout *TD;

37
lib/Target/MSP430/MSP430InstrInfo.h
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@@ -50,40 +50,41 @@ public:
/// such, whenever a client has an instance of instruction info, it should /// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method). /// always be able to get register info as well (through this method).
/// ///
virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } const TargetRegisterInfo &getRegisterInfo() const { return RI; }
void copyPhysReg(MachineBasicBlock &MBB, void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL, MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,
bool KillSrc) const; bool KillSrc) const override;
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
unsigned SrcReg, bool isKill, unsigned SrcReg, bool isKill,
int FrameIndex, int FrameIndex,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const; const TargetRegisterInfo *TRI) const override;
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIdx, unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const; const TargetRegisterInfo *TRI) const override;
unsigned GetInstSizeInBytes(const MachineInstr *MI) const; unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
// Branch folding goodness // Branch folding goodness
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; bool
bool isUnpredicatedTerminator(const MachineInstr *MI) const; ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
bool AnalyzeBranch(MachineBasicBlock &MBB, bool AnalyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond, SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const; bool AllowModify) const override;
unsigned RemoveBranch(MachineBasicBlock &MBB) const; unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond, const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const; DebugLoc DL) const override;
}; };

11
lib/Target/MSP430/MSP430RegisterInfo.h
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@@ -36,18 +36,19 @@ public:
/// Code Generation virtual methods... /// Code Generation virtual methods...
const MCPhysReg * const MCPhysReg *
getCalleeSavedRegs(const MachineFunction *MF = nullptr) const; getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
BitVector getReservedRegs(const MachineFunction &MF) const; BitVector getReservedRegs(const MachineFunction &MF) const override;
const TargetRegisterClass* const TargetRegisterClass*
getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const; getPointerRegClass(const MachineFunction &MF,
unsigned Kind = 0) const override;
void eliminateFrameIndex(MachineBasicBlock::iterator II, void eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum, int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = nullptr) const; RegScavenger *RS = nullptr) const override;
// Debug information queries. // Debug information queries.
unsigned getFrameRegister(const MachineFunction &MF) const; unsigned getFrameRegister(const MachineFunction &MF) const override;
}; };
} // end namespace llvm } // end namespace llvm

4
lib/Target/MSP430/MSP430TargetMachine.cpp
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@@ -51,8 +51,8 @@ public:
return getTM<MSP430TargetMachine>(); return getTM<MSP430TargetMachine>();
} }
virtual bool addInstSelector(); bool addInstSelector() override;
virtual bool addPreEmitPass(); bool addPreEmitPass() override;
}; };
} // namespace } // namespace

16
lib/Target/MSP430/MSP430TargetMachine.h
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@@ -43,25 +43,25 @@ public:
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
virtual const TargetFrameLowering *getFrameLowering() const { const TargetFrameLowering *getFrameLowering() const override {
return &FrameLowering; return &FrameLowering;
} }
virtual const MSP430InstrInfo *getInstrInfo() const { return &InstrInfo; } const MSP430InstrInfo *getInstrInfo() const override { return &InstrInfo; }
virtual const DataLayout *getDataLayout() const { return &DL;} const DataLayout *getDataLayout() const override { return &DL;}
virtual const MSP430Subtarget *getSubtargetImpl() const { return &Subtarget; } const MSP430Subtarget *getSubtargetImpl() const override { return &Subtarget; }
virtual const TargetRegisterInfo *getRegisterInfo() const { const TargetRegisterInfo *getRegisterInfo() const override {
return &InstrInfo.getRegisterInfo(); return &InstrInfo.getRegisterInfo();
} }
virtual const MSP430TargetLowering *getTargetLowering() const { const MSP430TargetLowering *getTargetLowering() const override {
return &TLInfo; return &TLInfo;
} }
virtual const MSP430SelectionDAGInfo* getSelectionDAGInfo() const { const MSP430SelectionDAGInfo* getSelectionDAGInfo() const override {
return &TSInfo; return &TSInfo;
} }
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
}; // MSP430TargetMachine. }; // MSP430TargetMachine.
} // end namespace llvm } // end namespace llvm