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Change names from RA to something unique to get rid of naming conflicts with

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certain linkers...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36944 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2007-05-08 19:02:46 +00:00
parent 56184904cd
commit e23e00ddea
2 changed files with 42 additions and 38 deletions
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36
lib/CodeGen/RegAllocLinearScan.cpp
View File

@ -47,9 +47,9 @@ namespace {
static unsigned numIterations = 0; static unsigned numIterations = 0;
static unsigned numIntervals = 0; static unsigned numIntervals = 0;
struct VISIBILITY_HIDDEN RA : public MachineFunctionPass { struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass {
static char ID; static char ID;
RA() : MachineFunctionPass((intptr_t)&ID) {} RALinScan() : MachineFunctionPass((intptr_t)&ID) {}
typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr; typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
typedef std::vector<IntervalPtr> IntervalPtrs; typedef std::vector<IntervalPtr> IntervalPtrs;
@ -149,10 +149,10 @@ namespace {
} }
} }
}; };
char RA::ID = 0; char RALinScan::ID = 0;
} }
void RA::ComputeRelatedRegClasses() { void RALinScan::ComputeRelatedRegClasses() {
const MRegisterInfo &MRI = *mri_; const MRegisterInfo &MRI = *mri_;
// First pass, add all reg classes to the union, and determine at least one // First pass, add all reg classes to the union, and determine at least one
@ -187,7 +187,7 @@ void RA::ComputeRelatedRegClasses() {
RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]); RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
} }
bool RA::runOnMachineFunction(MachineFunction &fn) { bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
mf_ = &fn; mf_ = &fn;
tm_ = &fn.getTarget(); tm_ = &fn.getTarget();
mri_ = tm_->getRegisterInfo(); mri_ = tm_->getRegisterInfo();
@ -222,7 +222,7 @@ bool RA::runOnMachineFunction(MachineFunction &fn) {
/// initIntervalSets - initialize the interval sets. /// initIntervalSets - initialize the interval sets.
/// ///
void RA::initIntervalSets() void RALinScan::initIntervalSets()
{ {
assert(unhandled_.empty() && fixed_.empty() && assert(unhandled_.empty() && fixed_.empty() &&
active_.empty() && inactive_.empty() && active_.empty() && inactive_.empty() &&
@ -237,7 +237,7 @@ void RA::initIntervalSets()
} }
} }
void RA::linearScan() void RALinScan::linearScan()
{ {
// linear scan algorithm // linear scan algorithm
DOUT << "********** LINEAR SCAN **********\n"; DOUT << "********** LINEAR SCAN **********\n";
@ -317,7 +317,7 @@ void RA::linearScan()
/// processActiveIntervals - expire old intervals and move non-overlapping ones /// processActiveIntervals - expire old intervals and move non-overlapping ones
/// to the inactive list. /// to the inactive list.
void RA::processActiveIntervals(unsigned CurPoint) void RALinScan::processActiveIntervals(unsigned CurPoint)
{ {
DOUT << "\tprocessing active intervals:\n"; DOUT << "\tprocessing active intervals:\n";
@ -363,7 +363,7 @@ void RA::processActiveIntervals(unsigned CurPoint)
/// processInactiveIntervals - expire old intervals and move overlapping /// processInactiveIntervals - expire old intervals and move overlapping
/// ones to the active list. /// ones to the active list.
void RA::processInactiveIntervals(unsigned CurPoint) void RALinScan::processInactiveIntervals(unsigned CurPoint)
{ {
DOUT << "\tprocessing inactive intervals:\n"; DOUT << "\tprocessing inactive intervals:\n";
@ -412,16 +412,18 @@ static void updateSpillWeights(std::vector<float> &Weights,
Weights[*as] += weight; Weights[*as] += weight;
} }
static RA::IntervalPtrs::iterator FindIntervalInVector(RA::IntervalPtrs &IP, static
LiveInterval *LI) { RALinScan::IntervalPtrs::iterator
for (RA::IntervalPtrs::iterator I = IP.begin(), E = IP.end(); I != E; ++I) FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
I != E; ++I)
if (I->first == LI) return I; if (I->first == LI) return I;
return IP.end(); return IP.end();
} }
static void RevertVectorIteratorsTo(RA::IntervalPtrs &V, unsigned Point) { static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, unsigned Point){
for (unsigned i = 0, e = V.size(); i != e; ++i) { for (unsigned i = 0, e = V.size(); i != e; ++i) {
RA::IntervalPtr &IP = V[i]; RALinScan::IntervalPtr &IP = V[i];
LiveInterval::iterator I = std::upper_bound(IP.first->begin(), LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
IP.second, Point); IP.second, Point);
if (I != IP.first->begin()) --I; if (I != IP.first->begin()) --I;
@ -431,7 +433,7 @@ static void RevertVectorIteratorsTo(RA::IntervalPtrs &V, unsigned Point) {
/// assignRegOrStackSlotAtInterval - assign a register if one is available, or /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
/// spill. /// spill.
void RA::assignRegOrStackSlotAtInterval(LiveInterval* cur) void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
{ {
DOUT << "\tallocating current interval: "; DOUT << "\tallocating current interval: ";
@ -752,7 +754,7 @@ void RA::assignRegOrStackSlotAtInterval(LiveInterval* cur)
/// getFreePhysReg - return a free physical register for this virtual register /// getFreePhysReg - return a free physical register for this virtual register
/// interval if we have one, otherwise return 0. /// interval if we have one, otherwise return 0.
unsigned RA::getFreePhysReg(LiveInterval *cur) { unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
std::vector<unsigned> inactiveCounts(mri_->getNumRegs(), 0); std::vector<unsigned> inactiveCounts(mri_->getNumRegs(), 0);
unsigned MaxInactiveCount = 0; unsigned MaxInactiveCount = 0;
@ -821,5 +823,5 @@ unsigned RA::getFreePhysReg(LiveInterval *cur) {
} }
FunctionPass* llvm::createLinearScanRegisterAllocator() { FunctionPass* llvm::createLinearScanRegisterAllocator() {
return new RA(); return new RALinScan();
} }

34
lib/CodeGen/RegAllocLocal.cpp
View File

@ -42,10 +42,10 @@ namespace {
createLocalRegisterAllocator); createLocalRegisterAllocator);
class VISIBILITY_HIDDEN RA : public MachineFunctionPass { class VISIBILITY_HIDDEN RALocal : public MachineFunctionPass {
public: public:
static char ID; static char ID;
RA() : MachineFunctionPass((intptr_t)&ID) {} RALocal() : MachineFunctionPass((intptr_t)&ID) {}
private: private:
const TargetMachine *TM; const TargetMachine *TM;
MachineFunction *MF; MachineFunction *MF;
@ -228,12 +228,12 @@ namespace {
void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
unsigned PhysReg); unsigned PhysReg);
}; };
char RA::ID = 0; char RALocal::ID = 0;
} }
/// getStackSpaceFor - This allocates space for the specified virtual register /// getStackSpaceFor - This allocates space for the specified virtual register
/// to be held on the stack. /// to be held on the stack.
int RA::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { int RALocal::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
// Find the location Reg would belong... // Find the location Reg would belong...
std::map<unsigned, int>::iterator I =StackSlotForVirtReg.lower_bound(VirtReg); std::map<unsigned, int>::iterator I =StackSlotForVirtReg.lower_bound(VirtReg);
@ -253,7 +253,7 @@ int RA::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
/// removePhysReg - This method marks the specified physical register as no /// removePhysReg - This method marks the specified physical register as no
/// longer being in use. /// longer being in use.
/// ///
void RA::removePhysReg(unsigned PhysReg) { void RALocal::removePhysReg(unsigned PhysReg) {
PhysRegsUsed[PhysReg] = -1; // PhyReg no longer used PhysRegsUsed[PhysReg] = -1; // PhyReg no longer used
std::vector<unsigned>::iterator It = std::vector<unsigned>::iterator It =
@ -267,7 +267,8 @@ void RA::removePhysReg(unsigned PhysReg) {
/// virtual register slot specified by VirtReg. It then updates the RA data /// virtual register slot specified by VirtReg. It then updates the RA data
/// structures to indicate the fact that PhysReg is now available. /// structures to indicate the fact that PhysReg is now available.
/// ///
void RA::spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, void RALocal::spillVirtReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg) { unsigned VirtReg, unsigned PhysReg) {
assert(VirtReg && "Spilling a physical register is illegal!" assert(VirtReg && "Spilling a physical register is illegal!"
" Must not have appropriate kill for the register or use exists beyond" " Must not have appropriate kill for the register or use exists beyond"
@ -300,7 +301,7 @@ void RA::spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
/// then the request is ignored if the physical register does not contain a /// then the request is ignored if the physical register does not contain a
/// virtual register. /// virtual register.
/// ///
void RA::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I, void RALocal::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
unsigned PhysReg, bool OnlyVirtRegs) { unsigned PhysReg, bool OnlyVirtRegs) {
if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used! if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used!
assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!"); assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!");
@ -334,7 +335,7 @@ void RA::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
/// that PhysReg is the proper container for VirtReg now. The physical /// that PhysReg is the proper container for VirtReg now. The physical
/// register must not be used for anything else when this is called. /// register must not be used for anything else when this is called.
/// ///
void RA::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) { void RALocal::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!"); assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!");
// Update information to note the fact that this register was just used, and // Update information to note the fact that this register was just used, and
// it holds VirtReg. // it holds VirtReg.
@ -348,7 +349,7 @@ void RA::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
/// and available for use. This also includes checking to see if aliased /// and available for use. This also includes checking to see if aliased
/// registers are all free... /// registers are all free...
/// ///
bool RA::isPhysRegAvailable(unsigned PhysReg) const { bool RALocal::isPhysRegAvailable(unsigned PhysReg) const {
if (PhysRegsUsed[PhysReg] != -1) return false; if (PhysRegsUsed[PhysReg] != -1) return false;
// If the selected register aliases any other allocated registers, it is // If the selected register aliases any other allocated registers, it is
@ -364,7 +365,7 @@ bool RA::isPhysRegAvailable(unsigned PhysReg) const {
/// getFreeReg - Look to see if there is a free register available in the /// getFreeReg - Look to see if there is a free register available in the
/// specified register class. If not, return 0. /// specified register class. If not, return 0.
/// ///
unsigned RA::getFreeReg(const TargetRegisterClass *RC) { unsigned RALocal::getFreeReg(const TargetRegisterClass *RC) {
// Get iterators defining the range of registers that are valid to allocate in // Get iterators defining the range of registers that are valid to allocate in
// this class, which also specifies the preferred allocation order. // this class, which also specifies the preferred allocation order.
TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF); TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
@ -383,7 +384,8 @@ unsigned RA::getFreeReg(const TargetRegisterClass *RC) {
/// use. If there is currently a value in it, it is either moved out of the way /// use. If there is currently a value in it, it is either moved out of the way
/// or spilled to memory. /// or spilled to memory.
/// ///
void RA::liberatePhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, void RALocal::liberatePhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I,
unsigned PhysReg) { unsigned PhysReg) {
spillPhysReg(MBB, I, PhysReg); spillPhysReg(MBB, I, PhysReg);
} }
@ -393,7 +395,7 @@ void RA::liberatePhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
/// register. If all compatible physical registers are used, this method spills /// register. If all compatible physical registers are used, this method spills
/// the last used virtual register to the stack, and uses that register. /// the last used virtual register to the stack, and uses that register.
/// ///
unsigned RA::getReg(MachineBasicBlock &MBB, MachineInstr *I, unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I,
unsigned VirtReg) { unsigned VirtReg) {
const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
@ -470,7 +472,7 @@ unsigned RA::getReg(MachineBasicBlock &MBB, MachineInstr *I,
/// subsequent instructions can use the reloaded value. This method returns the /// subsequent instructions can use the reloaded value. This method returns the
/// modified instruction. /// modified instruction.
/// ///
MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
unsigned OpNum) { unsigned OpNum) {
unsigned VirtReg = MI->getOperand(OpNum).getReg(); unsigned VirtReg = MI->getOperand(OpNum).getReg();
@ -522,7 +524,7 @@ MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
// loop over each instruction // loop over each instruction
MachineBasicBlock::iterator MII = MBB.begin(); MachineBasicBlock::iterator MII = MBB.begin();
const TargetInstrInfo &TII = *TM->getInstrInfo(); const TargetInstrInfo &TII = *TM->getInstrInfo();
@ -776,7 +778,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
/// runOnMachineFunction - Register allocate the whole function /// runOnMachineFunction - Register allocate the whole function
/// ///
bool RA::runOnMachineFunction(MachineFunction &Fn) { bool RALocal::runOnMachineFunction(MachineFunction &Fn) {
DOUT << "Machine Function " << "\n"; DOUT << "Machine Function " << "\n";
MF = &Fn; MF = &Fn;
TM = &Fn.getTarget(); TM = &Fn.getTarget();
@ -812,5 +814,5 @@ bool RA::runOnMachineFunction(MachineFunction &Fn) {
} }
FunctionPass *llvm::createLocalRegisterAllocator() { FunctionPass *llvm::createLocalRegisterAllocator() {
return new RA(); return new RALocal();
} }