6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-11-03 14:21:30 +00:00
Code Issues Projects Releases Wiki Activity

R600/SI: cleanup literal handling v3

Browse Source 
Seems to be allot simpler, and also paves the
way for further improvements.

v2: rebased on master, use 0 in BUFFER_LOAD_FORMAT_XYZW,
    use VGPR0 in dummy EXP, avoid compiler warning, break
    after encoding the first literal.
v3: correctly use V_ADD_F32_e64

This is a candidate for the stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175354 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Christian Konig
2013-02-16 11:28:22 +00:00
parent 8e4eebcecf
commit e25e490793
10 changed files with 176 additions and 195 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
lib/Target/R600/SIISelLowering.cpp
View File

@@ -77,8 +77,8 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_ADD_F32_e64))
.addOperand(MI->getOperand(0))
.addOperand(MI->getOperand(1))
.addReg(AMDGPU::SREG_LIT_0)
.addReg(AMDGPU::SREG_LIT_0)
.addImm(0x80) // SRC1
.addImm(0x80) // SRC2
.addImm(0) // ABS
.addImm(1) // CLAMP
.addImm(0) // OMOD
@@ -90,8 +90,8 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_ADD_F32_e64))
.addOperand(MI->getOperand(0))
.addOperand(MI->getOperand(1))
.addReg(AMDGPU::SREG_LIT_0)
.addReg(AMDGPU::SREG_LIT_0)
.addImm(0x80) // SRC1
.addImm(0x80) // SRC2
.addImm(1) // ABS
.addImm(0) // CLAMP
.addImm(0) // OMOD
@@ -103,8 +103,8 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_ADD_F32_e64))
.addOperand(MI->getOperand(0))
.addOperand(MI->getOperand(1))
.addReg(AMDGPU::SREG_LIT_0)
.addReg(AMDGPU::SREG_LIT_0)
.addImm(0x80) // SRC1
.addImm(0x80) // SRC2
.addImm(0) // ABS
.addImm(0) // CLAMP
.addImm(0) // OMOD
@@ -176,7 +176,7 @@ void SITargetLowering::LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB,
BuildMI(BB, I, BB.findDebugLoc(I),
TII->get(AMDGPU::V_CMP_GT_F32_e32),
VCC)
.addReg(AMDGPU::SREG_LIT_0)
.addImm(0)
.addOperand(MI->getOperand(1));
BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CNDMASK_B32_e32))