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Code Issues Projects Releases Wiki Activity

Move getCommonSubClass() into TRI.

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It will soon need the context.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140896 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2011-09-30 22:18:51 +00:00
parent f9a4bb78da
commit e27e1ca3c9
8 changed files with 22 additions and 16 deletions
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7
lib/CodeGen/MachineRegisterInfo.cpp
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@@ -18,7 +18,7 @@
using namespace llvm;
MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI)
: IsSSA(true) {
: TRI(&TRI), IsSSA(true) {
VRegInfo.reserve(256);
RegAllocHints.reserve(256);
UsedPhysRegs.resize(TRI.getNumRegs());
@@ -54,7 +54,7 @@ MachineRegisterInfo::constrainRegClass(unsigned Reg,
const TargetRegisterClass *OldRC = getRegClass(Reg);
if (OldRC == RC)
return RC;
const TargetRegisterClass *NewRC = getCommonSubClass(OldRC, RC);
const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC);
if (!NewRC || NewRC == OldRC)
return NewRC;
if (NewRC->getNumRegs() < MinNumRegs)
@@ -66,7 +66,6 @@ MachineRegisterInfo::constrainRegClass(unsigned Reg,
bool
MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
const TargetInstrInfo *TII = TM.getInstrInfo();
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
const TargetRegisterClass *OldRC = getRegClass(Reg);
const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC);
@@ -86,7 +85,7 @@ MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
const TargetRegisterClass *OpRC =
TII->getRegClass(I->getDesc(), I.getOperandNo(), TRI);
if (OpRC)
NewRC = getCommonSubClass(NewRC, OpRC);
NewRC = TRI->getCommonSubClass(NewRC, OpRC);
if (!NewRC || NewRC == OldRC)
return false;
}