mirror of
https://github.com/c64scene-ar/llvm-6502.git
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[Hexagon] Adding XTYPE/COMPLEX instructions and cleaning up tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227607 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
cea6171bda
commit
e288ebf31b
@ -2469,6 +2469,43 @@ def M2_mpyud_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 1>;
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def M2_mpyud_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 1>;
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}
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//===----------------------------------------------------------------------===//
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// Template Class -- Vector Multipy
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// Used for complex multiply real or imaginary, dual multiply and even halfwords
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//===----------------------------------------------------------------------===//
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class T_M2_vmpy < string opc, bits<3> MajOp, bits<3> MinOp, bit hasShift,
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bit isRnd, bit isSat >
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: MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
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"$Rdd = "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
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#!if(isRnd,":rnd","")
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#!if(isSat,":sat",""),
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[] > {
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bits<5> Rdd;
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bits<5> Rss;
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bits<5> Rtt;
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let IClass = 0b1110;
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let Inst{27-24} = 0b1000;
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let Inst{23-21} = MajOp;
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let Inst{7-5} = MinOp;
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let Inst{4-0} = Rdd;
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let Inst{20-16} = Rss;
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let Inst{12-8} = Rtt;
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}
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// Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat
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let Defs = [USR_OVF], isCodeGenOnly = 0 in {
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def M2_vcmpy_s1_sat_i: T_M2_vmpy <"vcmpyi", 0b110, 0b110, 1, 0, 1>;
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def M2_vcmpy_s0_sat_i: T_M2_vmpy <"vcmpyi", 0b010, 0b110, 0, 0, 1>;
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}
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// Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat
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let isCodeGenOnly = 0 in {
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def M2_vcmpy_s1_sat_r: T_M2_vmpy <"vcmpyr", 0b101, 0b110, 1, 0, 1>;
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def M2_vcmpy_s0_sat_r: T_M2_vmpy <"vcmpyr", 0b001, 0b110, 0, 0, 1>;
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}
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let hasNewValue = 1, opNewValue = 0 in
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class T_MType_mpy <string mnemonic, bits<4> RegTyBits, RegisterClass RC,
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bits<3> MajOp, bits<3> MinOp, bit isSat = 0, bit isRnd = 0,
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@ -2495,6 +2532,9 @@ class T_MType_mpy <string mnemonic, bits<4> RegTyBits, RegisterClass RC,
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let Inst{4-0} = dst;
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}
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class T_MType_vrcmpy <string mnemonic, bits<3> MajOp, bits<3> MinOp, bit isHi>
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: T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, 1, 1, "", 1, isHi>;
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class T_MType_dd <string mnemonic, bits<3> MajOp, bits<3> MinOp,
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bit isSat = 0, bit isRnd = 0 >
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: T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, isSat, isRnd>;
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@ -2526,6 +2566,13 @@ def M2_hmmpyh_rs1 : T_MType_rr2 <"mpy", 0b101, 0b100, 1, 1, ".h">;
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def M2_hmmpyl_rs1 : T_MType_rr2 <"mpy", 0b111, 0b100, 1, 1, ".l">;
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}
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let isCodeGenOnly = 0 in {
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def M2_cmpyrs_s0 : T_MType_rr2 <"cmpy", 0b001, 0b110, 1, 1>;
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def M2_cmpyrs_s1 : T_MType_rr2 <"cmpy", 0b101, 0b110, 1, 1>;
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def M2_cmpyrsc_s0 : T_MType_rr2 <"cmpy", 0b011, 0b110, 1, 1, "*">;
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def M2_cmpyrsc_s1 : T_MType_rr2 <"cmpy", 0b111, 0b110, 1, 1, "*">;
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}
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// V4 Instructions
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let isCodeGenOnly = 0 in {
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def M2_vraddh : T_MType_dd <"vraddh", 0b001, 0b111, 0>;
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@ -2761,6 +2808,55 @@ def A2_vrsadub_acc: T_XTYPE_Vect_acc <"vrsadub", 0b010, 0b010, 0>;
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let isCodeGenOnly = 0 in
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def M2_vabsdiffh: T_XTYPE_Vect_diff<0b011, "vabsdiffh">;
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// Vector reduce complex multiply real or imaginary:
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// Rdd[+]=vrcmpy[ir](Rss,Rtt[*])
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let isCodeGenOnly = 0 in {
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def M2_vrcmpyi_s0: T_XTYPE_Vect <"vrcmpyi", 0b000, 0b000, 0>;
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def M2_vrcmpyi_s0c: T_XTYPE_Vect <"vrcmpyi", 0b010, 0b000, 1>;
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def M2_vrcmaci_s0: T_XTYPE_Vect_acc <"vrcmpyi", 0b000, 0b000, 0>;
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def M2_vrcmaci_s0c: T_XTYPE_Vect_acc <"vrcmpyi", 0b010, 0b000, 1>;
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}
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let isCodeGenOnly = 0 in {
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def M2_vrcmpyr_s0: T_XTYPE_Vect <"vrcmpyr", 0b000, 0b001, 0>;
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def M2_vrcmpyr_s0c: T_XTYPE_Vect <"vrcmpyr", 0b011, 0b001, 1>;
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def M2_vrcmacr_s0: T_XTYPE_Vect_acc <"vrcmpyr", 0b000, 0b001, 0>;
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def M2_vrcmacr_s0c: T_XTYPE_Vect_acc <"vrcmpyr", 0b011, 0b001, 1>;
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}
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//===----------------------------------------------------------------------===//
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// Template Class -- Vector Multipy with accumulation.
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// Used for complex multiply real or imaginary, dual multiply and even halfwords
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//===----------------------------------------------------------------------===//
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let Defs = [USR_OVF] in
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class T_M2_vmpy_acc_sat < string opc, bits<3> MajOp, bits<3> MinOp,
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bit hasShift, bit isRnd >
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: MInst <(outs DoubleRegs:$Rxx),
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(ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
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"$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
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#!if(isRnd,":rnd","")#":sat",
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[], "$dst2 = $Rxx",M_tc_3x_SLOT23 > {
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bits<5> Rxx;
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bits<5> Rss;
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bits<5> Rtt;
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let IClass = 0b1110;
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let Inst{27-24} = 0b1010;
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let Inst{23-21} = MajOp;
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let Inst{7-5} = MinOp;
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let Inst{4-0} = Rxx;
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let Inst{20-16} = Rss;
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let Inst{12-8} = Rtt;
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}
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// Vector complex multiply real or imaginary with accumulation
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// Rxx+=vcmpy[ir](Rss,Rtt):sat
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let isCodeGenOnly = 0 in {
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def M2_vcmac_s0_sat_r: T_M2_vmpy_acc_sat <"vcmpyr", 0b001, 0b100, 0, 0>;
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def M2_vcmac_s0_sat_i: T_M2_vmpy_acc_sat <"vcmpyi", 0b010, 0b100, 0, 0>;
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}
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//===----------------------------------------------------------------------===//
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// Template Class -- Multiply signed/unsigned halfwords with and without
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// saturation and rounding
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@ -2890,6 +2986,47 @@ def M2_dpmpyss_nac_s0 : T_XTYPE_mpy64_acc < "mpy", "-", 0b001, 0b000, 0, 0, 0>;
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def M2_dpmpyuu_acc_s0 : T_XTYPE_mpy64_acc < "mpyu", "+", 0b010, 0b000, 0, 0, 0>;
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def M2_dpmpyuu_nac_s0 : T_XTYPE_mpy64_acc < "mpyu", "-", 0b011, 0b000, 0, 0, 0>;
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}
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// Complex multiply real or imaginary
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// Rxx=cmpy[ir](Rs,Rt)
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let isCodeGenOnly = 0 in {
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def M2_cmpyi_s0 : T_XTYPE_mpy64 < "cmpyi", 0b000, 0b001, 0, 0, 0>;
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def M2_cmpyr_s0 : T_XTYPE_mpy64 < "cmpyr", 0b000, 0b010, 0, 0, 0>;
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}
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// Rxx+=cmpy[ir](Rs,Rt)
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let isCodeGenOnly = 0 in {
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def M2_cmaci_s0 : T_XTYPE_mpy64_acc < "cmpyi", "+", 0b000, 0b001, 0, 0, 0>;
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def M2_cmacr_s0 : T_XTYPE_mpy64_acc < "cmpyr", "+", 0b000, 0b010, 0, 0, 0>;
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}
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// Complex multiply
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// Rdd=cmpy(Rs,Rt)[:<<]:sat
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let isCodeGenOnly = 0 in {
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def M2_cmpys_s0 : T_XTYPE_mpy64 < "cmpy", 0b000, 0b110, 1, 0, 0>;
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def M2_cmpys_s1 : T_XTYPE_mpy64 < "cmpy", 0b100, 0b110, 1, 1, 0>;
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}
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// Rdd=cmpy(Rs,Rt*)[:<<]:sat
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let isCodeGenOnly = 0 in {
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def M2_cmpysc_s0 : T_XTYPE_mpy64 < "cmpy", 0b010, 0b110, 1, 0, 1>;
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def M2_cmpysc_s1 : T_XTYPE_mpy64 < "cmpy", 0b110, 0b110, 1, 1, 1>;
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}
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// Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat
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let isCodeGenOnly = 0 in {
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def M2_cmacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b000, 0b110, 1, 0, 0>;
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def M2_cnacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b000, 0b111, 1, 0, 0>;
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def M2_cmacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b100, 0b110, 1, 1, 0>;
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def M2_cnacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b100, 0b111, 1, 1, 0>;
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}
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// Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat
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let isCodeGenOnly = 0 in {
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def M2_cmacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b010, 0b110, 1, 0, 1>;
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def M2_cnacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b010, 0b111, 1, 0, 1>;
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def M2_cmacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b110, 0b110, 1, 1, 1>;
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def M2_cnacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b110, 0b111, 1, 1, 1>;
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}
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def: Pat<(i64 (mul (i64 (anyext (i32 IntRegs:$src1))),
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(i64 (anyext (i32 IntRegs:$src2))))),
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@ -3741,6 +3878,10 @@ def S2_interleave : T_S2op_3 <"interleave", 0b11, 0b101>;
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def S2_deinterleave : T_S2op_3 <"deinterleave", 0b11, 0b100>;
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}
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// Vector Complex conjugate
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let isCodeGenOnly = 0 in
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def A2_vconj : T_S2op_3 <"vconj", 0b10, 0b111, 1>;
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// Vector absolute value halfwords with and without saturation
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// Rdd64=vabsh(Rss64)[:sat]
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let isCodeGenOnly = 0 in {
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@ -5411,6 +5552,31 @@ let Defs = [USR_OVF], isCodeGenOnly = 0 in {
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def S2_asl_r_r_sat : T_S3op_shift32_Sat<"asl", 0b10>;
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}
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let hasNewValue = 1, hasSideEffects = 0 in
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class T_S3op_8 <string opc, bits<3> MinOp, bit isSat, bit isRnd, bit hasShift, bit hasSplat = 0>
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: SInst < (outs IntRegs:$Rd),
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(ins DoubleRegs:$Rss, IntRegs:$Rt),
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"$Rd = "#opc#"($Rss, $Rt"#!if(hasSplat, "*", "")#")"
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#!if(hasShift, ":<<1", "")
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#!if(isRnd, ":rnd", "")
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#!if(isSat, ":sat", ""),
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[], "", S_3op_tc_1_SLOT23 > {
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bits<5> Rd;
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bits<5> Rss;
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bits<5> Rt;
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let IClass = 0b1100;
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let Inst{27-24} = 0b0101;
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let Inst{20-16} = Rss;
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let Inst{12-8} = Rt;
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let Inst{7-5} = MinOp;
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let Inst{4-0} = Rd;
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}
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let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23, isCodeGenOnly = 0 in
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def S2_vcrotate : T_S3op_shiftVect < "vcrotate", 0b11, 0b00>;
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//===----------------------------------------------------------------------===//
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// Template class for 'insert bitfield' instructions
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//===----------------------------------------------------------------------===//
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@ -195,3 +195,62 @@ def : Pat<(callv3nr tglobaladdr:$dst),
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(CALLv3nr tglobaladdr:$dst)>, Requires<[HasV3T]>;
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def : Pat<(callv3nr texternalsym:$dst),
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(CALLv3nr texternalsym:$dst)>, Requires<[HasV3T]>;
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//===----------------------------------------------------------------------===//
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// :raw form of vrcmpys:hi/lo insns
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//===----------------------------------------------------------------------===//
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// Vector reduce complex multiply by scalar.
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let Defs = [USR_OVF], hasSideEffects = 0 in
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class T_vrcmpRaw<string HiLo, bits<3>MajOp>:
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MInst<(outs DoubleRegs:$Rdd),
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(ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
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"$Rdd = vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, []> {
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bits<5> Rdd;
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bits<5> Rss;
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bits<5> Rtt;
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let IClass = 0b1110;
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let Inst{27-24} = 0b1000;
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let Inst{23-21} = MajOp;
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let Inst{20-16} = Rss;
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let Inst{12-8} = Rtt;
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let Inst{7-5} = 0b100;
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let Inst{4-0} = Rdd;
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}
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let isCodeGenOnly = 0 in {
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def M2_vrcmpys_s1_h: T_vrcmpRaw<"hi", 0b101>;
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def M2_vrcmpys_s1_l: T_vrcmpRaw<"lo", 0b111>;
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}
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// Vector reduce complex multiply by scalar with accumulation.
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let Defs = [USR_OVF], hasSideEffects = 0 in
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class T_vrcmpys_acc<string HiLo, bits<3>MajOp>:
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MInst <(outs DoubleRegs:$Rxx),
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(ins DoubleRegs:$_src_, DoubleRegs:$Rss, DoubleRegs:$Rtt),
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"$Rxx += vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, [],
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"$Rxx = $_src_"> {
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bits<5> Rxx;
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bits<5> Rss;
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bits<5> Rtt;
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let IClass = 0b1110;
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let Inst{27-24} = 0b1010;
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let Inst{23-21} = MajOp;
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let Inst{20-16} = Rss;
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let Inst{12-8} = Rtt;
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let Inst{7-5} = 0b100;
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let Inst{4-0} = Rxx;
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}
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let isCodeGenOnly = 0 in {
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def M2_vrcmpys_acc_s1_h: T_vrcmpys_acc<"hi", 0b101>;
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def M2_vrcmpys_acc_s1_l: T_vrcmpys_acc<"lo", 0b111>;
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}
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let isCodeGenOnly = 0 in {
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def M2_vrcmpys_s1rp_h : T_MType_vrcmpy <"vrcmpys", 0b101, 0b110, 1>;
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def M2_vrcmpys_s1rp_l : T_MType_vrcmpy <"vrcmpys", 0b101, 0b111, 0>;
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}
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@ -1741,6 +1741,19 @@ let hasNewValue = 1, isCodeGenOnly = 0 in {
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def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5Imm>;
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}
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// Complex add/sub halfwords/words
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let Defs = [USR_OVF], isCodeGenOnly = 0 in {
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def S4_vxaddsubh : T_S3op_64 < "vxaddsubh", 0b01, 0b100, 0, 1>;
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def S4_vxaddsubw : T_S3op_64 < "vxaddsubw", 0b01, 0b000, 0, 1>;
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def S4_vxsubaddh : T_S3op_64 < "vxsubaddh", 0b01, 0b110, 0, 1>;
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def S4_vxsubaddw : T_S3op_64 < "vxsubaddw", 0b01, 0b010, 0, 1>;
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}
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let Defs = [USR_OVF], isCodeGenOnly = 0 in {
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def S4_vxaddsubhr : T_S3op_64 < "vxaddsubh", 0b11, 0b000, 0, 1, 1, 1>;
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def S4_vxsubaddhr : T_S3op_64 < "vxsubaddh", 0b11, 0b010, 0, 1, 1, 1>;
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}
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let Itinerary = M_tc_3x_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in {
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def M4_mac_up_s1_sat: T_MType_acc_rr<"+= mpy", 0b011, 0b000, 0, [], 0, 1, 1>;
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def M4_nac_up_s1_sat: T_MType_acc_rr<"-= mpy", 0b011, 0b001, 0, [], 0, 1, 1>;
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@ -1769,6 +1782,53 @@ def M4_xor_xacc
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let Inst{4-0} = Rxx;
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}
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// Rotate and reduce bytes
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// Rdd=vrcrotate(Rss,Rt,#u2)
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let hasSideEffects = 0, isCodeGenOnly = 0 in
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def S4_vrcrotate
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: SInst <(outs DoubleRegs:$Rdd),
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(ins DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
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"$Rdd = vrcrotate($Rss, $Rt, #$u2)",
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[], "", S_3op_tc_3x_SLOT23> {
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bits<5> Rdd;
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bits<5> Rss;
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bits<5> Rt;
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bits<2> u2;
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let IClass = 0b1100;
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let Inst{27-22} = 0b001111;
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let Inst{20-16} = Rss;
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let Inst{13} = u2{1};
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let Inst{12-8} = Rt;
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let Inst{7-6} = 0b11;
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let Inst{5} = u2{0};
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let Inst{4-0} = Rdd;
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}
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// Rotate and reduce bytes with accumulation
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// Rxx+=vrcrotate(Rss,Rt,#u2)
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let hasSideEffects = 0, isCodeGenOnly = 0 in
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def S4_vrcrotate_acc
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: SInst <(outs DoubleRegs:$Rxx),
|
||||
(ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
|
||||
"$Rxx += vrcrotate($Rss, $Rt, #$u2)", [],
|
||||
"$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
|
||||
bits<5> Rxx;
|
||||
bits<5> Rss;
|
||||
bits<5> Rt;
|
||||
bits<2> u2;
|
||||
|
||||
let IClass = 0b1100;
|
||||
|
||||
let Inst{27-21} = 0b1011101;
|
||||
let Inst{20-16} = Rss;
|
||||
let Inst{13} = u2{1};
|
||||
let Inst{12-8} = Rt;
|
||||
let Inst{5} = u2{0};
|
||||
let Inst{4-0} = Rxx;
|
||||
}
|
||||
|
||||
|
||||
// Vector reduce conditional negate halfwords
|
||||
let hasSideEffects = 0, isCodeGenOnly = 0 in
|
||||
@ -2284,6 +2344,12 @@ let hasNewValue = 1, Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23,
|
||||
isCodeGenOnly = 0 in
|
||||
def A4_round_rr_sat : T_S3op_3 < "round", IntRegs, 0b11, 0b11, 1>;
|
||||
|
||||
// Rd=[cmpyiwh|cmpyrwh](Rss,Rt):<<1:rnd:sat
|
||||
let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23, isCodeGenOnly = 0 in {
|
||||
def M4_cmpyi_wh : T_S3op_8<"cmpyiwh", 0b100, 1, 1, 1>;
|
||||
def M4_cmpyr_wh : T_S3op_8<"cmpyrwh", 0b110, 1, 1, 1>;
|
||||
}
|
||||
|
||||
// Rdd=[add|sub](Rss,Rtt,Px):carry
|
||||
let isPredicateLate = 1, hasSideEffects = 0 in
|
||||
class T_S3op_carry <string mnemonic, bits<3> MajOp>
|
||||
|
||||
@ -765,6 +765,12 @@ def S5_asrhub_rnd_sat_goodsyntax
|
||||
: SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, u4Imm:$u4),
|
||||
"$Rd = vasrhub($Rss, #$u4):rnd:sat">, Requires<[HasV5T]>;
|
||||
|
||||
// Complex multiply 32x16
|
||||
let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23, isCodeGenOnly = 0 in {
|
||||
def M4_cmpyi_whc : T_S3op_8<"cmpyiwh", 0b101, 1, 1, 1, 1>;
|
||||
def M4_cmpyr_whc : T_S3op_8<"cmpyrwh", 0b111, 1, 1, 1, 1>;
|
||||
}
|
||||
|
||||
// Classify floating-point value
|
||||
let isFP = 1, isCodeGenOnly = 0 in
|
||||
def F2_sfclass : T_TEST_BIT_IMM<"sfclass", 0b111>;
|
||||
|
||||
@ -1,5 +1,7 @@
|
||||
# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
|
||||
# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
|
||||
# Hexagon Programmer's Reference Manual 11.10.2 XTYPE/BIT
|
||||
|
||||
# Count leading
|
||||
0x11 0xc0 0x54 0x88
|
||||
# CHECK: r17 = clb(r21:20)
|
||||
0x51 0xc0 0x54 0x88
|
||||
@ -20,8 +22,12 @@
|
||||
# CHECK: r17 = cl1(r21)
|
||||
0xf1 0xc0 0x15 0x8c
|
||||
# CHECK: r17 = normamt(r21)
|
||||
|
||||
# Count population
|
||||
0x71 0xc0 0x74 0x88
|
||||
# CHECK: r17 = popcount(r21:20)
|
||||
|
||||
# Count trailing
|
||||
0x51 0xc0 0xf4 0x88
|
||||
# CHECK: r17 = ct0(r21:20)
|
||||
0x91 0xc0 0xf4 0x88
|
||||
@ -30,6 +36,8 @@
|
||||
# CHECK: r17 = ct0(r21)
|
||||
0xb1 0xc0 0x55 0x8c
|
||||
# CHECK: r17 = ct1(r21)
|
||||
|
||||
# Extract bitfield
|
||||
0xf0 0xdf 0x54 0x81
|
||||
# CHECK: r17:16 = extractu(r21:20, #31, #23)
|
||||
0xf0 0xdf 0x54 0x8a
|
||||
@ -46,6 +54,8 @@
|
||||
# CHECK: r17 = extractu(r21, r31:30)
|
||||
0x51 0xde 0x15 0xc9
|
||||
# CHECK: r17 = extract(r21, r31:30)
|
||||
|
||||
# Insert bitfield
|
||||
0xf0 0xdf 0x54 0x83
|
||||
# CHECK: r17:16 = insert(r21:20, #31, #23)
|
||||
0xf1 0xdf 0x55 0x8f
|
||||
@ -54,20 +64,30 @@
|
||||
# CHECK: r17 = insert(r21, r31:30)
|
||||
0x10 0xde 0x14 0xca
|
||||
# CHECK: r17:16 = insert(r21:20, r31:30)
|
||||
|
||||
# Interleave/deinterleave
|
||||
0x90 0xc0 0xd4 0x80
|
||||
# CHECK: r17:16 = deinterleave(r21:20)
|
||||
0xb0 0xc0 0xd4 0x80
|
||||
# CHECK: r17:16 = interleave(r21:20)
|
||||
|
||||
# Linear feedback-shift iteration
|
||||
0xd0 0xde 0x94 0xc1
|
||||
# CHECK: r17:16 = lfs(r21:20, r31:30)
|
||||
|
||||
# Masked parity
|
||||
0x11 0xde 0x14 0xd0
|
||||
# CHECK: r17 = parity(r21:20, r31:30)
|
||||
0x11 0xdf 0xf5 0xd5
|
||||
# CHECK: r17 = parity(r21, r31)
|
||||
|
||||
# Bit reverse
|
||||
0xd0 0xc0 0xd4 0x80
|
||||
# CHECK: r17:16 = brev(r21:20)
|
||||
0xd1 0xc0 0x55 0x8c
|
||||
# CHECK: r17 = brev(r21)
|
||||
|
||||
# Set/clear/toggle bit
|
||||
0x11 0xdf 0xd5 0x8c
|
||||
# CHECK: r17 = setbit(r21, #31)
|
||||
0x31 0xdf 0xd5 0x8c
|
||||
@ -80,10 +100,14 @@
|
||||
# CHECK: r17 = clrbit(r21, r31)
|
||||
0x91 0xdf 0x95 0xc6
|
||||
# CHECK: r17 = togglebit(r21, r31)
|
||||
|
||||
# Split bitfield
|
||||
0x90 0xdf 0xd5 0x88
|
||||
# CHECK: r17:16 = bitsplit(r21, #31)
|
||||
0x10 0xdf 0x35 0xd4
|
||||
# CHECK: r17:16 = bitsplit(r21, r31)
|
||||
|
||||
# Table index
|
||||
0xf1 0xcd 0x15 0x87
|
||||
# CHECK: r17 = tableidxb(r21, #7, #13):raw
|
||||
0xf1 0xcd 0x55 0x87
|
||||
|
||||
128
test/MC/Disassembler/Hexagon/xtype_complex.txt
Normal file
128
test/MC/Disassembler/Hexagon/xtype_complex.txt
Normal file
@ -0,0 +1,128 @@
|
||||
# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
|
||||
# Hexagon Programmer's Reference Manual 11.10.3 XTYPE/COMPLEX
|
||||
|
||||
# Complex add/sub halfwords
|
||||
0x90 0xde 0x54 0xc1
|
||||
# CHECK: r17:16 = vxaddsubh(r21:20, r31:30):sat
|
||||
0xd0 0xde 0x54 0xc1
|
||||
# CHECK: r17:16 = vxsubaddh(r21:20, r31:30):sat
|
||||
0x10 0xde 0xd4 0xc1
|
||||
# CHECK: r17:16 = vxaddsubh(r21:20, r31:30):rnd:>>1:sat
|
||||
0x50 0xde 0xd4 0xc1
|
||||
# CHECK: r17:16 = vxsubaddh(r21:20, r31:30):rnd:>>1:sat
|
||||
|
||||
# Complex add/sub words
|
||||
0x10 0xde 0x54 0xc1
|
||||
# CHECK: r17:16 = vxaddsubw(r21:20, r31:30):sat
|
||||
0x50 0xde 0x54 0xc1
|
||||
# CHECK: r17:16 = vxsubaddw(r21:20, r31:30):sat
|
||||
|
||||
# Complex multiply
|
||||
0xd0 0xdf 0x15 0xe5
|
||||
# CHECK: r17:16 = cmpy(r21, r31):sat
|
||||
0xd0 0xdf 0x95 0xe5
|
||||
# CHECK: r17:16 = cmpy(r21, r31):<<1:sat
|
||||
0xd0 0xdf 0x55 0xe5
|
||||
# CHECK: r17:16 = cmpy(r21, r31*):sat
|
||||
0xd0 0xdf 0xd5 0xe5
|
||||
# CHECK: r17:16 = cmpy(r21, r31*):<<1:sat
|
||||
0xd0 0xdf 0x15 0xe7
|
||||
# CHECK: r17:16 += cmpy(r21, r31):sat
|
||||
0xd0 0xdf 0x95 0xe7
|
||||
# CHECK: r17:16 += cmpy(r21, r31):<<1:sat
|
||||
0xf0 0xdf 0x15 0xe7
|
||||
# CHECK: r17:16 -= cmpy(r21, r31):sat
|
||||
0xf0 0xdf 0x95 0xe7
|
||||
# CHECK: r17:16 -= cmpy(r21, r31):<<1:sat
|
||||
0xd0 0xdf 0x55 0xe7
|
||||
# CHECK: r17:16 += cmpy(r21, r31*):sat
|
||||
0xd0 0xdf 0xd5 0xe7
|
||||
# CHECK: r17:16 += cmpy(r21, r31*):<<1:sat
|
||||
0xf0 0xdf 0x55 0xe7
|
||||
# CHECK: r17:16 -= cmpy(r21, r31*):sat
|
||||
0xf0 0xdf 0xd5 0xe7
|
||||
# CHECK: r17:16 -= cmpy(r21, r31*):<<1:sat
|
||||
|
||||
# Complex multiply real or imaginary
|
||||
0x30 0xdf 0x15 0xe5
|
||||
# CHECK: r17:16 = cmpyi(r21, r31)
|
||||
0x50 0xdf 0x15 0xe5
|
||||
# CHECK: r17:16 = cmpyr(r21, r31)
|
||||
0x30 0xdf 0x15 0xe7
|
||||
# CHECK: r17:16 += cmpyi(r21, r31)
|
||||
0x50 0xdf 0x15 0xe7
|
||||
# CHECK: r17:16 += cmpyr(r21, r31)
|
||||
|
||||
# Complex multiply with round and pack
|
||||
0xd1 0xdf 0x35 0xed
|
||||
# CHECK: r17 = cmpy(r21, r31):rnd:sat
|
||||
0xd1 0xdf 0xb5 0xed
|
||||
# CHECK: r17 = cmpy(r21, r31):<<1:rnd:sat
|
||||
0xd1 0xdf 0x75 0xed
|
||||
# CHECK: r17 = cmpy(r21, r31*):rnd:sat
|
||||
0xd1 0xdf 0xf5 0xed
|
||||
# CHECK: r17 = cmpy(r21, r31*):<<1:rnd:sat
|
||||
|
||||
# Complex multiply 32x16
|
||||
0x91 0xdf 0x14 0xc5
|
||||
# CHECK: r17 = cmpyiwh(r21:20, r31):<<1:rnd:sat
|
||||
0xb1 0xdf 0x14 0xc5
|
||||
# CHECK: r17 = cmpyiwh(r21:20, r31*):<<1:rnd:sat
|
||||
0xd1 0xdf 0x14 0xc5
|
||||
# CHECK: r17 = cmpyrwh(r21:20, r31):<<1:rnd:sat
|
||||
0xf1 0xdf 0x14 0xc5
|
||||
# CHECK: r17 = cmpyrwh(r21:20, r31*):<<1:rnd:sat
|
||||
|
||||
# Vector complex multiply real or imaginary
|
||||
0xd0 0xde 0x34 0xe8
|
||||
# CHECK: r17:16 = vcmpyr(r21:20, r31:30):sat
|
||||
0xd0 0xde 0xb4 0xe8
|
||||
# CHECK: r17:16 = vcmpyr(r21:20, r31:30):<<1:sat
|
||||
0xd0 0xde 0x54 0xe8
|
||||
# CHECK: r17:16 = vcmpyi(r21:20, r31:30):sat
|
||||
0xd0 0xde 0xd4 0xe8
|
||||
# CHECK: r17:16 = vcmpyi(r21:20, r31:30):<<1:sat
|
||||
0x90 0xde 0x34 0xea
|
||||
# CHECK: r17:16 += vcmpyr(r21:20, r31:30):sat
|
||||
0x90 0xde 0x54 0xea
|
||||
# CHECK: r17:16 += vcmpyi(r21:20, r31:30):sat
|
||||
|
||||
# Vector complex conjugate
|
||||
0xf0 0xc0 0x94 0x80
|
||||
# CHECK: r17:16 = vconj(r21:20):sat
|
||||
|
||||
# Vector complex rotate
|
||||
0x10 0xdf 0xd4 0xc3
|
||||
# CHECK: r17:16 = vcrotate(r21:20, r31)
|
||||
|
||||
# Vector reduce complex multiply real or imaginary
|
||||
0x10 0xde 0x14 0xe8
|
||||
# CHECK: r17:16 = vrcmpyi(r21:20, r31:30)
|
||||
0x30 0xde 0x14 0xe8
|
||||
# CHECK: r17:16 = vrcmpyr(r21:20, r31:30)
|
||||
0x10 0xde 0x54 0xe8
|
||||
# CHECK: r17:16 = vrcmpyi(r21:20, r31:30*)
|
||||
0x30 0xde 0x74 0xe8
|
||||
# CHECK: r17:16 = vrcmpyr(r21:20, r31:30*)
|
||||
|
||||
# Vector reduce complex multiply by scalar
|
||||
0x90 0xde 0xb4 0xe8
|
||||
# CHECK: r17:16 = vrcmpys(r21:20, r31:30):<<1:sat:raw:hi
|
||||
0x90 0xde 0xf4 0xe8
|
||||
# CHECK: r17:16 = vrcmpys(r21:20, r31:30):<<1:sat:raw:lo
|
||||
0x90 0xde 0xb4 0xea
|
||||
# CHECK: r17:16 += vrcmpys(r21:20, r31:30):<<1:sat:raw:hi
|
||||
0x90 0xde 0xf4 0xea
|
||||
# CHECK: r17:16 += vrcmpys(r21:20, r31:30):<<1:sat:raw:lo
|
||||
|
||||
# Vector reduce complex multiply by scalar with round and pack
|
||||
0xd1 0xde 0xb4 0xe9
|
||||
# CHECK: r17 = vrcmpys(r21:20, r31:30):<<1:rnd:sat:raw:hi
|
||||
0xf1 0xde 0xb4 0xe9
|
||||
# CHECK: r17 = vrcmpys(r21:20, r31:30):<<1:rnd:sat:raw:lo
|
||||
|
||||
# Vector reduce complex rotate
|
||||
0xf0 0xff 0xd4 0xc3
|
||||
# CHECK: r17:16 = vrcrotate(r21:20, r31, #3)
|
||||
0x30 0xff 0xb4 0xcb
|
||||
# CHECK: r17:16 += vrcrotate(r21:20, r31, #3)
|
||||
Loading…
x
Reference in New Issue
Block a user