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[ARM64] Conditionalize CPU specific system registers on subtarget features

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207742 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bradley Smith
2014-05-01 10:25:36 +00:00
parent 4c715625d9
commit e29cd17aeb
7 changed files with 84 additions and 20 deletions
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12
lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
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@@ -601,11 +601,15 @@ static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm,
static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
uint64_t Address,
const void *Decoder) {
const ARM64Disassembler *Dis =
static_cast<const ARM64Disassembler *>(Decoder);
const MCSubtargetInfo &STI = Dis->getSubtargetInfo();
Imm |= 0x8000;
Inst.addOperand(MCOperand::CreateImm(Imm));
bool ValidNamed;
(void)ARM64SysReg::MRSMapper().toString(Imm, ValidNamed);
(void)ARM64SysReg::MRSMapper(STI.getFeatureBits()).toString(Imm, ValidNamed);
return ValidNamed ? Success : Fail;
}
@@ -613,11 +617,15 @@ static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
uint64_t Address,
const void *Decoder) {
const ARM64Disassembler *Dis =
static_cast<const ARM64Disassembler *>(Decoder);
const MCSubtargetInfo &STI = Dis->getSubtargetInfo();
Imm |= 0x8000;
Inst.addOperand(MCOperand::CreateImm(Imm));
bool ValidNamed;
(void)ARM64SysReg::MSRMapper().toString(Imm, ValidNamed);
(void)ARM64SysReg::MSRMapper(STI.getFeatureBits()).toString(Imm, ValidNamed);
return ValidNamed ? Success : Fail;
}