6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-06 23:32:27 +00:00
Code Issues Projects Releases Wiki Activity

[PowerPC] Don't ever expand BUILD_VECTOR of v2i64 with shuffles

Browse Source 
If we have two unique values for a v2i64 build vector, this will always result
in two vector loads if we expand using shuffles. Only one is necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205231 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2014-03-31 17:48:16 +00:00
parent adbf9764ae
commit e2b3751924
3 changed files with 20 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -8845,6 +8845,15 @@ bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
return false; return false;
} }
bool
PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
EVT VT , unsigned DefinedValues) const {
if (VT == MVT::v2i64)
return false;
return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
}
Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const { Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
if (DisableILPPref || PPCSubTarget.enableMachineScheduler()) if (DisableILPPref || PPCSubTarget.enableMachineScheduler())
return TargetLowering::getSchedulingPreference(N); return TargetLowering::getSchedulingPreference(N);

5
lib/Target/PowerPC/PPCISelLowering.h
View File

@ -477,6 +477,11 @@ namespace llvm {
/// expanded to fmul + fadd. /// expanded to fmul + fadd.
virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const; virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
// Should we expand the build vector with shuffles?
virtual bool
shouldExpandBuildVectorWithShuffles(EVT VT,
unsigned DefinedValues) const;
/// createFastISel - This method returns a target-specific FastISel object, /// createFastISel - This method returns a target-specific FastISel object,
/// or null if the target does not support "fast" instruction selection. /// or null if the target does not support "fast" instruction selection.
virtual FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, virtual FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,

11
test/CodeGen/PowerPC/vsx.ll
View File

@ -631,12 +631,13 @@ define <2 x i32> @test80(i32 %v) {
ret <2 x i32> %i ret <2 x i32> %i
; CHECK-LABEL: @test80 ; CHECK-LABEL: @test80
; CHECK: addi ; CHECK-DAG: addi [[R1:[0-9]+]], 3, 3
; CHECK: addi ; CHECK-DAG: addi [[R2:[0-9]+]], 1, -16
; CHECK: lxvd2x ; CHECK-DAG: addi [[R3:[0-9]+]], 3, 2
; CHECK: std [[R1]], 8([[R2]])
; CHECK: std [[R3]], -16(1)
; CHECK: lxvd2x 34, 0, [[R2]]
; CHECK-NOT: stxvd2x ; CHECK-NOT: stxvd2x
; FIXME: We still make one vector for each vector element and this shuffle them
; together instead of just composing one vector on the stack.
; CHECK: blr ; CHECK: blr
} }