6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-19 18:24:00 +00:00
Code Issues Projects Releases Wiki Activity

MachineOperand:

Browse Source 
- Add getParent() accessors.
  - Move SubReg out of the AuxInfo union, to make way for future changes.
  - Remove the getImmedValue/setImmedValue methods.
  - in some MachineOperand::Create* methods, stop initializing fields that are dead.

MachineInstr:
  - Delete one copy of the MachineInstr printing code, now there is only one dump
    format and one copy of the code.
  - Make MachineOperand use the parent field to get info about preg register names if
    no target info is otherwise available.
  - Move def/use/kill/dead flag printing to the machineoperand printer, so they are
    always printed for an operand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45460 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2007-12-30 21:31:53 +00:00
parent 1c3e1e2ed0
commit e3087890ac
3 changed files with 73 additions and 98 deletions
Download Patch File Download Diff File Expand all files Collapse all files

95
lib/CodeGen/MachineInstr.cpp
View File

@ -267,17 +267,47 @@ void MachineInstr::dump() const {
cerr << " " << *this;
}
/// print - Print the specified machine operand.
///
static void print(const MachineOperand &MO, std::ostream &OS,
const TargetMachine *TM) {
switch (MO.getType()) {
case MachineOperand::MO_Register:
if (MO.getReg() == 0 || MRegisterInfo::isVirtualRegister(MO.getReg()))
OS << "%reg" << MO.getReg();
else if (TM)
OS << "%" << TM->getRegisterInfo()->get(MO.getReg()).Name;
else
OS << "%mreg" << MO.getReg();
if (MO.isDef()) OS << "<d>";
else {
// If the instruction is embedded into a basic block, we can find the
// target
// info for the instruction.
if (TM == 0)
if (const MachineInstr *MI = MO.getParent())
if (const MachineBasicBlock *MBB = MI->getParent())
if (const MachineFunction *MF = MBB->getParent())
TM = &MF->getTarget();
if (TM)
OS << "%" << TM->getRegisterInfo()->get(MO.getReg()).Name;
else
OS << "%mreg" << MO.getReg();
}
if (MO.isDef() || MO.isKill() || MO.isDead() || MO.isImplicit()) {
OS << "<";
bool NeedComma = false;
if (MO.isImplicit()) {
OS << (MO.isDef() ? "imp-def" : "imp-use");
NeedComma = true;
} else if (MO.isDef()) {
OS << "def";
NeedComma = true;
}
if (MO.isKill() || MO.isDead()) {
if (NeedComma) OS << ",";
if (MO.isKill()) OS << "kill";
if (MO.isDead()) OS << "dead";
}
OS << ">";
}
break;
case MachineOperand::MO_Immediate:
OS << MO.getImm();
@ -314,75 +344,26 @@ static void print(const MachineOperand &MO, std::ostream &OS,
}
void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
// Specialize printing if op#0 is definition
unsigned StartOp = 0;
// Specialize printing if op#0 is definition
if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
::print(getOperand(0), OS, TM);
if (getOperand(0).isDead())
OS << "<dead>";
OS << " = ";
++StartOp; // Don't print this operand again!
}
if (TID)
OS << TID->Name;
OS << getInstrDescriptor()->Name;
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
const MachineOperand& mop = getOperand(i);
if (i != StartOp)
OS << ",";
OS << " ";
::print(mop, OS, TM);
if (mop.isRegister()) {
if (mop.isDef() || mop.isKill() || mop.isDead() || mop.isImplicit()) {
OS << "<";
bool NeedComma = false;
if (mop.isImplicit()) {
OS << (mop.isDef() ? "imp-def" : "imp-use");
NeedComma = true;
} else if (mop.isDef()) {
OS << "def";
NeedComma = true;
}
if (mop.isKill() || mop.isDead()) {
if (NeedComma)
OS << ",";
if (mop.isKill())
OS << "kill";
if (mop.isDead())
OS << "dead";
}
OS << ">";
}
}
::print(getOperand(i), OS, TM);
}
OS << "\n";
}
void MachineInstr::print(std::ostream &os) const {
// If the instruction is embedded into a basic block, we can find the target
// info for the instruction.
if (const MachineBasicBlock *MBB = getParent()) {
const MachineFunction *MF = MBB->getParent();
if (MF)
print(os, &MF->getTarget());
else
print(os, 0);
}
// Otherwise, print it out in the "raw" format without symbolic register names
// and such.
os << getInstrDescriptor()->Name;
for (unsigned i = 0, N = getNumOperands(); i < N; i++)
os << "\t" << getOperand(i);
os << "\n";
}
void MachineOperand::print(std::ostream &OS) const {
::print(*this, OS, 0);
}