MachineOperand:

- Add getParent() accessors.
  - Move SubReg out of the AuxInfo union, to make way for future changes.
  - Remove the getImmedValue/setImmedValue methods.
  - in some MachineOperand::Create* methods, stop initializing fields that are dead.

MachineInstr:
  - Delete one copy of the MachineInstr printing code, now there is only one dump
    format and one copy of the code.
  - Make MachineOperand use the parent field to get info about preg register names if
    no target info is otherwise available.
  - Move def/use/kill/dead flag printing to the machineoperand printer, so they are
    always printed for an operand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45460 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/CodeGen/MachineInstr.h

@@ -150,14 +150,9 @@ public:
   void print(std::ostream *OS, const TargetMachine *TM) const {
     if (OS) print(*OS, TM);
   }
-  void print(std::ostream &OS, const TargetMachine *TM) const;
+  void print(std::ostream &OS, const TargetMachine *TM = 0) const;
-  void print(std::ostream &OS) const;
   void print(std::ostream *OS) const { if (OS) print(*OS); }
   void dump() const;
-  friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr){
-    minstr.print(os);
-    return os;
-  }
 
   //===--------------------------------------------------------------------===//
   // Accessors to add operands when building up machine instructions.
@@ -202,7 +197,10 @@ private:
 //===----------------------------------------------------------------------===//
 // Debugging Support
 
-std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI);
+inline std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI) {
+  MI.print(OS);
+  return OS;
+}
 
 } // End llvm namespace
 

include/llvm/CodeGen/MachineOperand.h

@@ -46,7 +46,8 @@ private:
     MachineBasicBlock *MBB;   // For MO_MachineBasicBlock.
     const char *SymbolName;   // For MO_ExternalSymbol.
     unsigned RegNo;           // For MO_Register.
-    int64_t immedVal;         // For MO_Immediate and MO_*Index.
+    int64_t ImmVal;           // For MO_Immediate.
+    int Index;                // For MO_FrameIndex/CPI/JTI.
   } contents;
 
   /// ParentMI - This is the instruction that this operand is embedded into.
@@ -61,6 +62,10 @@ private:
   bool IsDead : 1;             // True if this is a reg def and the reg is dead
                                // immediately after the write. i.e. A register
                                // that is defined but never used.
+
+  /// SubReg - Subregister number, only valid for MO_Register.  A value of 0
+  /// indicates the MO_Register has no subReg.
+  unsigned char SubReg;
   
   /// auxInfo - auxiliary information used by the MachineOperand
   union {
@@ -68,9 +73,6 @@ private:
     /// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex
     int offset;
 
-    /// subReg - SubRegister number, only valid for MO_Register.  A value of 0
-    /// indicates the MO_Register has no subReg.
-    unsigned char subReg;
   } auxInfo;
   
   MachineOperand() : ParentMI(0) {}
@@ -89,6 +91,11 @@ public:
   ///
   MachineOperandType getType() const { return opType; }
 
+  /// getParent - Return the instruction that this operand belongs to.
+  ///
+  MachineInstr *getParent() { return ParentMI; }
+  const MachineInstr *getParent() const { return ParentMI; }
+  
   /// Accessors that tell you what kind of MachineOperand you're looking at.
   ///
   bool isRegister() const { return opType == MO_Register; }
@@ -102,13 +109,9 @@ public:
 
   int64_t getImm() const {
     assert(isImmediate() && "Wrong MachineOperand accessor");
-    return contents.immedVal;
+    return contents.ImmVal;
   }
   
-  int64_t getImmedValue() const {
-    assert(isImmediate() && "Wrong MachineOperand accessor");
-    return contents.immedVal;
-  }
   MachineBasicBlock *getMBB() const {
     assert(isMachineBasicBlock() && "Wrong MachineOperand accessor");
     return contents.MBB;
@@ -123,15 +126,15 @@ public:
   }
   int getFrameIndex() const {
     assert(isFrameIndex() && "Wrong MachineOperand accessor");
-    return (int)contents.immedVal;
+    return (int)contents.Index;
   }
   unsigned getConstantPoolIndex() const {
     assert(isConstantPoolIndex() && "Wrong MachineOperand accessor");
-    return (unsigned)contents.immedVal;
+    return (unsigned)contents.Index;
   }
   unsigned getJumpTableIndex() const {
     assert(isJumpTableIndex() && "Wrong MachineOperand accessor");
-    return (unsigned)contents.immedVal;
+    return (unsigned)contents.Index;
   }
   GlobalValue *getGlobal() const {
     assert(isGlobalAddress() && "Wrong MachineOperand accessor");
@@ -144,7 +147,7 @@ public:
   }
   unsigned getSubReg() const {
     assert(isRegister() && "Wrong MachineOperand accessor");
-    return (unsigned)auxInfo.subReg;
+    return (unsigned)SubReg;
   }
   const char *getSymbolName() const {
     assert(isExternalSymbol() && "Wrong MachineOperand accessor");
@@ -216,32 +219,27 @@ public:
     contents.RegNo = Reg;
   }
 
-  void setImmedValue(int64_t immVal) {
-    assert(isImmediate() && "Wrong MachineOperand mutator");
-    contents.immedVal = immVal;
-  }
   void setImm(int64_t immVal) {
     assert(isImmediate() && "Wrong MachineOperand mutator");
-    contents.immedVal = immVal;
+    contents.ImmVal = immVal;
   }
 
   void setOffset(int Offset) {
-    assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex() ||
+    assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex()) &&
-            isJumpTableIndex()) &&
         "Wrong MachineOperand accessor");
     auxInfo.offset = Offset;
   }
   void setSubReg(unsigned subReg) {
     assert(isRegister() && "Wrong MachineOperand accessor");
-    auxInfo.subReg = (unsigned char)subReg;
+    SubReg = (unsigned char)subReg;
   }
   void setConstantPoolIndex(unsigned Idx) {
     assert(isConstantPoolIndex() && "Wrong MachineOperand accessor");
-    contents.immedVal = Idx;
+    contents.Index = Idx;
   }
   void setJumpTableIndex(unsigned Idx) {
     assert(isJumpTableIndex() && "Wrong MachineOperand accessor");
-    contents.immedVal = Idx;
+    contents.Index = Idx;
   }
   
   /// isIdenticalTo - Return true if this operand is identical to the specified
@@ -250,10 +248,10 @@ public:
   
   /// ChangeToImmediate - Replace this operand with a new immediate operand of
   /// the specified value.  If an operand is known to be an immediate already,
-  /// the setImmedValue method should be used.
+  /// the setImm method should be used.
   void ChangeToImmediate(int64_t ImmVal) {
     opType = MO_Immediate;
-    contents.immedVal = ImmVal;
+    contents.ImmVal = ImmVal;
   }
 
   /// ChangeToRegister - Replace this operand with a new register operand of
@@ -267,13 +265,13 @@ public:
     IsImp = isImp;
     IsKill = isKill;
     IsDead = isDead;
+    SubReg = 0;
   }
   
   static MachineOperand CreateImm(int64_t Val) {
     MachineOperand Op;
     Op.opType = MachineOperand::MO_Immediate;
-    Op.contents.immedVal = Val;
+    Op.contents.ImmVal = Val;
-    Op.auxInfo.offset = 0;
     return Op;
   }
   static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
@@ -286,35 +284,32 @@ public:
     Op.IsKill = isKill;
     Op.IsDead = isDead;
     Op.contents.RegNo = Reg;
-    Op.auxInfo.subReg = SubReg;
+    Op.SubReg = SubReg;
     return Op;
   }
   static MachineOperand CreateMBB(MachineBasicBlock *MBB) {
     MachineOperand Op;
     Op.opType = MachineOperand::MO_MachineBasicBlock;
     Op.contents.MBB = MBB;
-    Op.auxInfo.offset = 0;
     return Op;
   }
   static MachineOperand CreateFI(unsigned Idx) {
     MachineOperand Op;
     Op.opType = MachineOperand::MO_FrameIndex;
-    Op.contents.immedVal = Idx;
+    Op.contents.Index = Idx;
-    Op.auxInfo.offset = 0;
     return Op;
   }
   static MachineOperand CreateCPI(unsigned Idx, int Offset) {
     MachineOperand Op;
     Op.opType = MachineOperand::MO_ConstantPoolIndex;
-    Op.contents.immedVal = Idx;
+    Op.contents.Index = Idx;
     Op.auxInfo.offset = Offset;
     return Op;
   }
   static MachineOperand CreateJTI(unsigned Idx) {
     MachineOperand Op;
     Op.opType = MachineOperand::MO_JumpTableIndex;
-    Op.contents.immedVal = Idx;
+    Op.contents.Index = Idx;
-    Op.auxInfo.offset = 0;
     return Op;
   }
   static MachineOperand CreateGA(GlobalValue *GV, int Offset) {
@@ -339,6 +334,7 @@ public:
     IsDead   = MO.IsDead;
     opType   = MO.opType;
     auxInfo  = MO.auxInfo;
+    SubReg   = MO.SubReg;
     ParentMI = MO.ParentMI;
     return *this;
   }

lib/CodeGen/MachineInstr.cpp

@@ -267,17 +267,47 @@ void MachineInstr::dump() const {
   cerr << "  " << *this;
 }
 
+/// print - Print the specified machine operand.
+///
 static void print(const MachineOperand &MO, std::ostream &OS,
                   const TargetMachine *TM) {
   switch (MO.getType()) {
   case MachineOperand::MO_Register:
     if (MO.getReg() == 0 || MRegisterInfo::isVirtualRegister(MO.getReg()))
       OS << "%reg" << MO.getReg();
-    else if (TM)
+    else {
-      OS << "%" << TM->getRegisterInfo()->get(MO.getReg()).Name;
+      // If the instruction is embedded into a basic block, we can find the
-    else
+      // target
-      OS << "%mreg" << MO.getReg();
+      // info for the instruction.
-    if (MO.isDef()) OS << "<d>";
+      if (TM == 0)
+        if (const MachineInstr *MI = MO.getParent())
+          if (const MachineBasicBlock *MBB = MI->getParent())
+            if (const MachineFunction *MF = MBB->getParent())
+              TM = &MF->getTarget();
+      
+      if (TM)
+        OS << "%" << TM->getRegisterInfo()->get(MO.getReg()).Name;
+      else
+        OS << "%mreg" << MO.getReg();
+    }
+      
+    if (MO.isDef() || MO.isKill() || MO.isDead() || MO.isImplicit()) {
+      OS << "<";
+      bool NeedComma = false;
+      if (MO.isImplicit()) {
+        OS << (MO.isDef() ? "imp-def" : "imp-use");
+        NeedComma = true;
+      } else if (MO.isDef()) {
+        OS << "def";
+        NeedComma = true;
+      }
+      if (MO.isKill() || MO.isDead()) {
+        if (NeedComma)    OS << ",";
+        if (MO.isKill()) OS << "kill";
+        if (MO.isDead()) OS << "dead";
+      }
+      OS << ">";
+    }
     break;
   case MachineOperand::MO_Immediate:
     OS << MO.getImm();
@@ -314,75 +344,26 @@ static void print(const MachineOperand &MO, std::ostream &OS,
 }
 
 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
+  // Specialize printing if op#0 is definition
   unsigned StartOp = 0;
-
-   // Specialize printing if op#0 is definition
   if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
     ::print(getOperand(0), OS, TM);
-    if (getOperand(0).isDead())
-      OS << "<dead>";
     OS << " = ";
     ++StartOp;   // Don't print this operand again!
   }
 
-  if (TID)
+  OS << getInstrDescriptor()->Name;
-    OS << TID->Name;
 
   for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
-    const MachineOperand& mop = getOperand(i);
     if (i != StartOp)
       OS << ",";
     OS << " ";
-    ::print(mop, OS, TM);
+    ::print(getOperand(i), OS, TM);
-
-    if (mop.isRegister()) {
-      if (mop.isDef() || mop.isKill() || mop.isDead() || mop.isImplicit()) {
-        OS << "<";
-        bool NeedComma = false;
-        if (mop.isImplicit()) {
-          OS << (mop.isDef() ? "imp-def" : "imp-use");
-          NeedComma = true;
-        } else if (mop.isDef()) {
-          OS << "def";
-          NeedComma = true;
-        }
-        if (mop.isKill() || mop.isDead()) {
-          if (NeedComma)
-            OS << ",";
-          if (mop.isKill())
-            OS << "kill";
-          if (mop.isDead())
-            OS << "dead";
-        }
-        OS << ">";
-      }
-    }
   }
 
   OS << "\n";
 }
 
-void MachineInstr::print(std::ostream &os) const {
-  // If the instruction is embedded into a basic block, we can find the target
-  // info for the instruction.
-  if (const MachineBasicBlock *MBB = getParent()) {
-    const MachineFunction *MF = MBB->getParent();
-    if (MF)
-      print(os, &MF->getTarget());
-    else
-      print(os, 0);
-  }
-
-  // Otherwise, print it out in the "raw" format without symbolic register names
-  // and such.
-  os << getInstrDescriptor()->Name;
-
-  for (unsigned i = 0, N = getNumOperands(); i < N; i++)
-    os << "\t" << getOperand(i);
-
-  os << "\n";
-}
-
 void MachineOperand::print(std::ostream &OS) const {
   ::print(*this, OS, 0);
 }