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Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143552 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-11-02 17:41:23 +00:00
parent 5a83264fa2
commit e31b42a6f5
1 changed files with 5 additions and 1 deletions
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6
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -1111,7 +1111,11 @@ static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
}
// Empty register lists are not allowed.
if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
uint32_t popcnt = CountPopulation_32(Val);
if (popcnt == 0) return MCDisassembler::Fail;
// and one-register lists are unpredictable.
else if (popcnt == 1) Check(S, MCDisassembler::SoftFail);
for (unsigned i = 0; i < 16; ++i) {
if (Val & (1 << i)) {
if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))