From e31b42a6f5598691498808673648211916bf4d0f Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Wed, 2 Nov 2011 17:41:23 +0000 Subject: [PATCH] Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143552 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 6927d2d053c..8dab1531321 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -1111,7 +1111,11 @@ static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, } // Empty register lists are not allowed. - if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; + uint32_t popcnt = CountPopulation_32(Val); + if (popcnt == 0) return MCDisassembler::Fail; + // and one-register lists are unpredictable. + else if (popcnt == 1) Check(S, MCDisassembler::SoftFail); + for (unsigned i = 0; i < 16; ++i) { if (Val & (1 << i)) { if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))