diff --git a/lib/Target/X86/X86InstrArithmetic.td b/lib/Target/X86/X86InstrArithmetic.td
index 3540fc31257..d56763ea9d2 100644
--- a/lib/Target/X86/X86InstrArithmetic.td
+++ b/lib/Target/X86/X86InstrArithmetic.td
@@ -266,7 +266,7 @@ def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem,                      // GR64 = [mem64]*I8
 
 
 // unsigned division/remainder
-let hasSideEffects = 1 in { // so that we don't speculatively execute
+let hasSideEffects = 0 in {
 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
 def DIV8r  : I<0xF6, MRM6r, (outs),  (ins GR8:$src),    // AX/r8 = AL,AH
                "div{b}\t$src", [], IIC_DIV8_REG>;
diff --git a/test/CodeGen/X86/early-ifcvt.ll b/test/CodeGen/X86/early-ifcvt.ll
index b3a20c3ee0b..2e1852d3e3a 100644
--- a/test/CodeGen/X86/early-ifcvt.ll
+++ b/test/CodeGen/X86/early-ifcvt.ll
@@ -142,35 +142,3 @@ save_state_and_return:
 }
 
 declare void @BZ2_bz__AssertH__fail()
-
-
-; Make sure we don't speculate on div/idiv instructions
-; CHECK: test_idiv
-; CHECK-NOT: cmov
-define i32 @test_idiv(i32 %a, i32 %b) nounwind uwtable readnone ssp {
-  %1 = icmp eq i32 %b, 0
-  br i1 %1, label %4, label %2
-
-; <label>:2                                       ; preds = %0
-  %3 = sdiv i32 %a, %b
-  br label %4
-
-; <label>:4                                       ; preds = %0, %2
-  %5 = phi i32 [ %3, %2 ], [ %a, %0 ]
-  ret i32 %5
-}
-
-; CHECK: test_div
-; CHECK-NOT: cmov
-define i32 @test_div(i32 %a, i32 %b) nounwind uwtable readnone ssp {
-  %1 = icmp eq i32 %b, 0
-  br i1 %1, label %4, label %2
-
-; <label>:2                                       ; preds = %0
-  %3 = udiv i32 %a, %b
-  br label %4
-
-; <label>:4                                       ; preds = %0, %2
-  %5 = phi i32 [ %3, %2 ], [ %a, %0 ]
-  ret i32 %5
-}