From e35d3bb84e73b85d4c96fc4ad75120541844b080 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sun, 16 Oct 2005 00:36:38 +0000 Subject: [PATCH] update this a little bit to talk about the dag combiner and remove inaccuracies. This still doesn't talk about autogen much git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23757 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/CodeGenerator.html | 70 ++++++++++++++++++++++++----------------- 1 file changed, 42 insertions(+), 28 deletions(-) diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html index a62dbedcdb1..a4a6ea0dbae 100644 --- a/docs/CodeGenerator.html +++ b/docs/CodeGenerator.html @@ -15,7 +15,8 @@
  • Introduction
    • @@ -46,8 +47,10 @@ Construction
  • SelectionDAG Legalize Phase
  • SelectionDAG Optimization - Phase
    • + Phase: the DAG Combiner
  • SelectionDAG Select Phase
    • +
  • SelectionDAG Scheduling and Emission + Phase
  • Future directions for the SelectionDAG
    • @@ -631,23 +634,15 @@ explains how they work and some of the rationale behind their design.

    Instruction Selection is the process of translating LLVM code presented to the code generator into target-specific machine instructions. There are several well-known ways to do this in the literature. In LLVM there are two main forms: -the old-style 'simple' instruction selector (which effectively peephole selects -each LLVM instruction into a series of machine instructions), and the new -SelectionDAG based instruction selector. +the SelectionDAG based instruction selector framework and an old-style 'simple' +instruction selector (which effectively peephole selects each LLVM instruction +into a series of machine instructions). We recommend that all targets use the +SelectionDAG infrastructure.

    -

    The 'simple' instruction selectors are tedious to write, require a lot of -boiler plate code, and are difficult to get correct. Additionally, any -optimizations written for a simple instruction selector cannot be used by other -targets. For this reason, LLVM is moving to a new SelectionDAG based -instruction selector, which is described in this section. If you are starting a -new port, we recommend that you write the instruction selector using the -SelectionDAG infrastructure.

    - -

    In time, most of the target-specific code for instruction selection will be -auto-generated from the target description (*.td) files. For now, -however, the Select Phase must still be -written by hand.

    +

    Portions of the DAG instruction selector are generated from the target +description files (*.td) files. Eventually, we aim for the entire +instruction selector to be generated from these .td files.

    @@ -744,8 +739,12 @@ SelectionDAG-based instruction selection consists of the following steps: eliminate inefficiencies introduced by legalization.
  • Select instructions from DAG - Finally, the target instruction selector matches the DAG operations to target - instructions, emitting them and building the MachineFunction being - compiled.
    • + instructions. This process translates the target-independent input DAG into + another DAG of target instructions. +
  • SelectionDAG Scheduling and Emission + - The last phase assigns a linear order to the instructions in the + target-instruction DAG and emits them into the MachineFunction being + compiled. This step uses traditional prepass scheduling techniques.

    • After all of these steps are complete, the SelectionDAG is destroyed and the @@ -822,7 +821,8 @@ a DAG.

    - SelectionDAG Optimization Phase + SelectionDAG Optimization Phase: the DAG + Combiner
    @@ -838,8 +838,9 @@ special cases.

    -One important class of optimizations that this pass will do in the future is -optimizing inserted sign and zero extension instructions. Here are some good +One important class of optimizations performed is optimizing inserted sign and +zero extension instructions. We currently use ad-hoc techniques, but could move +to more rigorous techniques in the future. Here are some good papers on the subject:

    @@ -875,6 +876,23 @@ want to make the Select phase as simple and mechanical as possible.

    + +
    + SelectionDAG Scheduling and Emission Phase +
    + +
    + +

    The scheduling phase takes the DAG of target instructions from the selection +phase and assigns an order. The scheduler can pick an order depending on +various constraints of the machines (i.e. order for minimal register pressure or +try to cover instruction latencies). Once an order is established, the DAG is +converted to a list of MachineInstrs and the +Selection DAG is destroyed. +

    + +
    +
    Future directions for the SelectionDAG @@ -883,12 +901,8 @@ want to make the Select phase as simple and mechanical as possible.

      -
    1. Optional whole-function selection.
      2. -
    2. Select is a graph translation phase.
      3. -
    3. Place the machine instructions resulting from Select according to register -pressure or a schedule.
      4. -
    4. DAG Scheduling.
      5. -
    5. Auto-generate the Select phase from the target description (*.td) files. +
    6. Optional function-at-a-time selection.
      7. +
    7. Auto-generate entire selector from .td file.