From e368b460a206fafa0d31d5d059b1779b94f7df8c Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Fri, 18 Jun 2010 14:22:04 +0000 Subject: [PATCH] Eliminate unnecessary uses of getZExtValue(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106279 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/SelectionDAGNodes.h | 1 + include/llvm/IntrinsicInst.h | 2 +- lib/Analysis/ConstantFolding.cpp | 2 +- lib/CodeGen/DwarfEHPrepare.cpp | 2 +- lib/CodeGen/SelectionDAG/FastISel.cpp | 2 +- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 4 ++-- lib/Target/ARM/ARMISelDAGToDAG.cpp | 2 +- lib/Target/CellSPU/SPUISelLowering.cpp | 2 +- lib/Target/PIC16/PIC16ISelLowering.cpp | 6 +++--- lib/Target/PowerPC/PPCISelLowering.cpp | 6 +++--- lib/Target/Sparc/SparcISelLowering.cpp | 6 +++--- lib/Target/TargetLoweringObjectFile.cpp | 2 +- lib/Target/X86/X86FastISel.cpp | 2 +- lib/Target/X86/X86ISelLowering.cpp | 4 ++-- 14 files changed, 22 insertions(+), 21 deletions(-) diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index 316ae26ac6a..50d853cb46e 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -1082,6 +1082,7 @@ public: uint64_t getZExtValue() const { return Value->getZExtValue(); } int64_t getSExtValue() const { return Value->getSExtValue(); } + bool isOne() const { return Value->isOne(); } bool isNullValue() const { return Value->isNullValue(); } bool isAllOnesValue() const { return Value->isAllOnesValue(); } diff --git a/include/llvm/IntrinsicInst.h b/include/llvm/IntrinsicInst.h index 5b0e90f5cc0..4402b121593 100644 --- a/include/llvm/IntrinsicInst.h +++ b/include/llvm/IntrinsicInst.h @@ -136,7 +136,7 @@ namespace llvm { return cast(const_cast(getOperand(5))); } bool isVolatile() const { - return getVolatileCst()->getZExtValue() != 0; + return !getVolatileCst()->isZero(); } /// getDest - This is just like getRawDest, but it strips off any cast diff --git a/lib/Analysis/ConstantFolding.cpp b/lib/Analysis/ConstantFolding.cpp index 37cda022102..1f4538ab937 100644 --- a/lib/Analysis/ConstantFolding.cpp +++ b/lib/Analysis/ConstantFolding.cpp @@ -208,7 +208,7 @@ static bool IsConstantOffsetFromGlobal(Constant *C, GlobalValue *&GV, i != e; ++i, ++GTI) { ConstantInt *CI = dyn_cast(*i); if (!CI) return false; // Index isn't a simple constant? - if (CI->getZExtValue() == 0) continue; // Not adding anything. + if (CI->isZero()) continue; // Not adding anything. if (const StructType *ST = dyn_cast(*GTI)) { // N = N + Offset diff --git a/lib/CodeGen/DwarfEHPrepare.cpp b/lib/CodeGen/DwarfEHPrepare.cpp index 399fb8d6575..66739316258 100644 --- a/lib/CodeGen/DwarfEHPrepare.cpp +++ b/lib/CodeGen/DwarfEHPrepare.cpp @@ -210,7 +210,7 @@ bool DwarfEHPrepare::IsACleanupSelector(IntrinsicInst *II) { if (Val + 4 == NumOps) { if (ConstantInt *FinalVal = dyn_cast(II->getOperand(NumOps - 1))) - return (FinalVal->getZExtValue() == 0); + return FinalVal->isZero(); } } } diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp index 2c4a7c54c44..5cb739ef4d5 100644 --- a/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -345,7 +345,7 @@ bool FastISel::SelectGetElementPtr(const User *I) { // If this is a constant subscript, handle it quickly. if (const ConstantInt *CI = dyn_cast(Idx)) { - if (CI->getZExtValue() == 0) continue; + if (CI->isZero()) continue; uint64_t Offs = TD.getTypeAllocSize(Ty)*cast(CI)->getSExtValue(); N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 833173f2440..f43c4e4e7e4 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -2734,7 +2734,7 @@ void SelectionDAGBuilder::visitGetElementPtr(const User &I) { // If this is a constant subscript, handle it quickly. if (const ConstantInt *CI = dyn_cast(Idx)) { - if (CI->getZExtValue() == 0) continue; + if (CI->isZero()) continue; uint64_t Offs = TD->getTypeAllocSize(Ty)*cast(CI)->getSExtValue(); SDValue OffsVal; @@ -4367,7 +4367,7 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { SDValue Arg = getValue(I.getOperand(0)); EVT Ty = Arg.getValueType(); - if (CI->getZExtValue() == 0) + if (CI->isZero()) Res = DAG.getConstant(-1ULL, Ty); else Res = DAG.getConstant(0, Ty); diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 9128889b14b..35a983e5d2d 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -536,7 +536,7 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDNode *Op, SDValue N, DebugLoc dl = Op->getDebugLoc(); if (N.getOpcode() != ISD::ADD) { ConstantSDNode *NC = dyn_cast(N); - if (!NC || NC->getZExtValue() != 0) + if (!NC || !NC->isNullValue()) return false; Base = Offset = N; diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index affd066876f..65eecbaf562 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -2867,7 +2867,7 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const case SPUISD::IndirectAddr: { if (!ST->usingLargeMem() && Op0.getOpcode() == SPUISD::AFormAddr) { ConstantSDNode *CN = dyn_cast(N->getOperand(1)); - if (CN != 0 && CN->getZExtValue() == 0) { + if (CN != 0 && CN->isNullValue()) { // (SPUindirect (SPUaform , 0), 0) -> // (SPUaform , 0) diff --git a/lib/Target/PIC16/PIC16ISelLowering.cpp b/lib/Target/PIC16/PIC16ISelLowering.cpp index f479f4626fd..d4369bc5075 100644 --- a/lib/Target/PIC16/PIC16ISelLowering.cpp +++ b/lib/Target/PIC16/PIC16ISelLowering.cpp @@ -1791,14 +1791,14 @@ static PIC16CC::CondCodes IntCCToPIC16CC(ISD::CondCode CC) { static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode CC, unsigned &SPCC) { if (isa(RHS) && - cast(RHS)->getZExtValue() == 0 && + cast(RHS)->isNullValue() && CC == ISD::SETNE && (LHS.getOpcode() == PIC16ISD::SELECT_ICC && LHS.getOperand(3).getOpcode() == PIC16ISD::SUBCC) && isa(LHS.getOperand(0)) && isa(LHS.getOperand(1)) && - cast(LHS.getOperand(0))->getZExtValue() == 1 && - cast(LHS.getOperand(1))->getZExtValue() == 0) { + cast(LHS.getOperand(0))->isOne() && + cast(LHS.getOperand(1))->isNullValue()) { SDValue CMPCC = LHS.getOperand(3); SPCC = cast(LHS.getOperand(2))->getZExtValue(); LHS = CMPCC.getOperand(0); diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 10b516aa133..63802fab1a9 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -5042,19 +5042,19 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, default: break; case PPCISD::SHL: if (ConstantSDNode *C = dyn_cast(N->getOperand(0))) { - if (C->getZExtValue() == 0) // 0 << V -> 0. + if (C->isNullValue()) // 0 << V -> 0. return N->getOperand(0); } break; case PPCISD::SRL: if (ConstantSDNode *C = dyn_cast(N->getOperand(0))) { - if (C->getZExtValue() == 0) // 0 >>u V -> 0. + if (C->isNullValue()) // 0 >>u V -> 0. return N->getOperand(0); } break; case PPCISD::SRA: if (ConstantSDNode *C = dyn_cast(N->getOperand(0))) { - if (C->getZExtValue() == 0 || // 0 >>s V -> 0. + if (C->isNullValue() || // 0 >>s V -> 0. C->isAllOnesValue()) // -1 >>s V -> -1. return N->getOperand(0); } diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index f47e53acbfc..aafd1b4b4aa 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -737,7 +737,7 @@ void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode CC, unsigned &SPCC) { if (isa(RHS) && - cast(RHS)->getZExtValue() == 0 && + cast(RHS)->isNullValue() && CC == ISD::SETNE && ((LHS.getOpcode() == SPISD::SELECT_ICC && LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || @@ -745,8 +745,8 @@ static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && isa(LHS.getOperand(0)) && isa(LHS.getOperand(1)) && - cast(LHS.getOperand(0))->getZExtValue() == 1 && - cast(LHS.getOperand(1))->getZExtValue() == 0) { + cast(LHS.getOperand(0))->isOne() && + cast(LHS.getOperand(1))->isNullValue()) { SDValue CMPCC = LHS.getOperand(3); SPCC = cast(LHS.getOperand(2))->getZExtValue(); LHS = CMPCC.getOperand(0); diff --git a/lib/Target/TargetLoweringObjectFile.cpp b/lib/Target/TargetLoweringObjectFile.cpp index b9372d04bb1..dd7b532bbfb 100644 --- a/lib/Target/TargetLoweringObjectFile.cpp +++ b/lib/Target/TargetLoweringObjectFile.cpp @@ -101,7 +101,7 @@ static bool IsNullTerminatedString(const Constant *C) { ConstantInt *Null = dyn_cast(CVA->getOperand(ATy->getNumElements()-1)); - if (Null == 0 || Null->getZExtValue() != 0) + if (Null == 0 || !Null->isZero()) return false; // Not null terminated. // Verify that the null doesn't occur anywhere else in the string. diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp index 4ec69657b3a..7bbe6ab5751 100644 --- a/lib/Target/X86/X86FastISel.cpp +++ b/lib/Target/X86/X86FastISel.cpp @@ -1210,7 +1210,7 @@ bool X86FastISel::X86VisitIntrinsicCall(const IntrinsicInst &I) { unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); BuildMI(MBB, DL, TII.get(OpC), ResultReg). - addImm(CI->getZExtValue() == 0 ? -1ULL : 0); + addImm(CI->isZero() ? -1ULL : 0); UpdateValueMap(&I, ResultReg); return true; } diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index b74af619685..2c8e74861af 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -3185,7 +3185,7 @@ unsigned X86::getShufflePALIGNRImmediate(SDNode *N) { /// constant +0.0. bool X86::isZeroNode(SDValue Elt) { return ((isa(Elt) && - cast(Elt)->getZExtValue() == 0) || + cast(Elt)->isNullValue()) || (isa(Elt) && cast(Elt)->getValueAPF().isPosZero())); } @@ -6229,7 +6229,7 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && Op1.getOpcode() == ISD::Constant && - cast(Op1)->getZExtValue() == 0 && + cast(Op1)->isNullValue() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); if (NewSetCC.getNode())