diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index d4cac4d3bac..2d228eabb9d 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -286,11 +286,11 @@ let usesCustomInserter = 1, Uses = [FCC] in { // Section A.3 - Synthetic Instructions, p. 85 // special cases of JMPL: let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in { - let rd = O7.Num, rs1 = G0.Num in + let rd = 0, rs1 = 15 in def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val), "jmp %o7+$val", [(retflag simm13:$val)]>; - let rd = I7.Num, rs1 = G0.Num in + let rd = 0, rs1 = 31 in def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val), "jmp %i7+$val", []>; } diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td index a59c4426f03..b239f80db51 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.td +++ b/lib/Target/Sparc/SparcRegisterInfo.td @@ -11,8 +11,8 @@ // Declarations that describe the Sparc register file //===----------------------------------------------------------------------===// -class SparcReg : Register { - field bits<5> Num; +class SparcReg Enc, string n> : Register { + let HWEncoding = Enc; let Namespace = "SP"; } @@ -27,16 +27,13 @@ def sub_odd : SubRegIndex<32, 32>; // Registers are identified with 5-bit ID numbers. // Ri - 32-bit integer registers -class Ri num, string n> : SparcReg { - let Num = num; -} +class Ri Enc, string n> : SparcReg; + // Rf - 32-bit floating-point registers -class Rf num, string n> : SparcReg { - let Num = num; -} +class Rf Enc, string n> : SparcReg; + // Rd - Slots in the FP register file for 64-bit floating-point values. -class Rd num, string n, list subregs> : SparcReg { - let Num = num; +class Rd Enc, string n, list subregs> : SparcReg { let SubRegs = subregs; let SubRegIndices = [sub_even, sub_odd]; let CoveredBySubRegs = 1;