mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-09-24 23:28:41 +00:00
Added support for overloading intrinsics (atomics) based on pointers
to different address spaces. This alters the naming scheme for those intrinsics, e.g., atomic.load.add.i32 => atomic.load.add.i32.p0i32 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54195 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Mon P Wang
@@ -5788,14 +5788,15 @@ i1 <device> )
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<div class="doc_text">
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<h5>Syntax:</h5>
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<p>
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This is an overloaded intrinsic. You can use <tt>llvm.atomic.cmp.swap</tt> on any
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integer bit width. Not all targets support all bit widths however.</p>
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This is an overloaded intrinsic. You can use <tt>llvm.atomic.cmp.swap</tt> on
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any integer bit width and for different address spaces. Not all targets
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support all bit widths however.</p>
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<pre>
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declare i8 @llvm.atomic.cmp.swap.i8( i8* <ptr>, i8 <cmp>, i8 <val> )
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declare i16 @llvm.atomic.cmp.swap.i16( i16* <ptr>, i16 <cmp>, i16 <val> )
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declare i32 @llvm.atomic.cmp.swap.i32( i32* <ptr>, i32 <cmp>, i32 <val> )
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declare i64 @llvm.atomic.cmp.swap.i64( i64* <ptr>, i64 <cmp>, i64 <val> )
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declare i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* <ptr>, i8 <cmp>, i8 <val> )
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declare i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* <ptr>, i16 <cmp>, i16 <val> )
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declare i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* <ptr>, i32 <cmp>, i32 <val> )
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declare i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* <ptr>, i64 <cmp>, i64 <val> )
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</pre>
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<h5>Overview:</h5>
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@@ -5827,13 +5828,13 @@ declare i64 @llvm.atomic.cmp.swap.i64( i64* <ptr>, i64 <cmp>, i64 &l
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store i32 4, %ptr
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%val1 = add i32 4, 4
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%result1 = call i32 @llvm.atomic.cmp.swap.i32( i32* %ptr, i32 4, %val1 )
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%result1 = call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %ptr, i32 4, %val1 )
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<i>; yields {i32}:result1 = 4</i>
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%stored1 = icmp eq i32 %result1, 4 <i>; yields {i1}:stored1 = true</i>
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%memval1 = load i32* %ptr <i>; yields {i32}:memval1 = 8</i>
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%val2 = add i32 1, 1
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%result2 = call i32 @llvm.atomic.cmp.swap.i32( i32* %ptr, i32 5, %val2 )
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%result2 = call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %ptr, i32 5, %val2 )
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<i>; yields {i32}:result2 = 8</i>
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%stored2 = icmp eq i32 %result2, 5 <i>; yields {i1}:stored2 = false</i>
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@@ -5852,10 +5853,10 @@ declare i64 @llvm.atomic.cmp.swap.i64( i64* <ptr>, i64 <cmp>, i64 &l
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This is an overloaded intrinsic. You can use <tt>llvm.atomic.swap</tt> on any
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integer bit width. Not all targets support all bit widths however.</p>
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<pre>
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declare i8 @llvm.atomic.swap.i8( i8* <ptr>, i8 <val> )
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declare i16 @llvm.atomic.swap.i16( i16* <ptr>, i16 <val> )
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declare i32 @llvm.atomic.swap.i32( i32* <ptr>, i32 <val> )
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declare i64 @llvm.atomic.swap.i64( i64* <ptr>, i64 <val> )
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declare i8 @llvm.atomic.swap.i8.p0i8( i8* <ptr>, i8 <val> )
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declare i16 @llvm.atomic.swap.i16.p0i16( i16* <ptr>, i16 <val> )
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declare i32 @llvm.atomic.swap.i32.p0i32( i32* <ptr>, i32 <val> )
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declare i64 @llvm.atomic.swap.i64.p0i64( i64* <ptr>, i64 <val> )
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</pre>
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<h5>Overview:</h5>
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@@ -5886,13 +5887,13 @@ declare i64 @llvm.atomic.swap.i64( i64* <ptr>, i64 <val> )
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store i32 4, %ptr
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%val1 = add i32 4, 4
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%result1 = call i32 @llvm.atomic.swap.i32( i32* %ptr, i32 %val1 )
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%result1 = call i32 @llvm.atomic.swap.i32.p0i32( i32* %ptr, i32 %val1 )
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<i>; yields {i32}:result1 = 4</i>
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%stored1 = icmp eq i32 %result1, 4 <i>; yields {i1}:stored1 = true</i>
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%memval1 = load i32* %ptr <i>; yields {i32}:memval1 = 8</i>
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%val2 = add i32 1, 1
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%result2 = call i32 @llvm.atomic.swap.i32( i32* %ptr, i32 %val2 )
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%result2 = call i32 @llvm.atomic.swap.i32.p0i32( i32* %ptr, i32 %val2 )
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<i>; yields {i32}:result2 = 8</i>
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%stored2 = icmp eq i32 %result2, 8 <i>; yields {i1}:stored2 = true</i>
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@@ -5911,10 +5912,10 @@ declare i64 @llvm.atomic.swap.i64( i64* <ptr>, i64 <val> )
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This is an overloaded intrinsic. You can use <tt>llvm.atomic.load.add</tt> on any
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integer bit width. Not all targets support all bit widths however.</p>
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<pre>
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declare i8 @llvm.atomic.load.add.i8.( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.load.add.i16.( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.load.add.i32.( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.load.add.i64.( i64* <ptr>, i64 <delta> )
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declare i8 @llvm.atomic.load.add.i8..p0i8( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.load.add.i16..p0i16( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.load.add.i32..p0i32( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.load.add.i64..p0i64( i64* <ptr>, i64 <delta> )
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</pre>
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<h5>Overview:</h5>
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@@ -5941,11 +5942,11 @@ declare i64 @llvm.atomic.load.add.i64.( i64* <ptr>, i64 <delta> )
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<pre>
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%ptr = malloc i32
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store i32 4, %ptr
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%result1 = call i32 @llvm.atomic.load.add.i32( i32* %ptr, i32 4 )
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%result1 = call i32 @llvm.atomic.load.add.i32.p0i32( i32* %ptr, i32 4 )
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<i>; yields {i32}:result1 = 4</i>
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%result2 = call i32 @llvm.atomic.load.add.i32( i32* %ptr, i32 2 )
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%result2 = call i32 @llvm.atomic.load.add.i32.p0i32( i32* %ptr, i32 2 )
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<i>; yields {i32}:result2 = 8</i>
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%result3 = call i32 @llvm.atomic.load.add.i32( i32* %ptr, i32 5 )
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%result3 = call i32 @llvm.atomic.load.add.i32.p0i32( i32* %ptr, i32 5 )
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<i>; yields {i32}:result3 = 10</i>
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%memval1 = load i32* %ptr <i>; yields {i32}:memval1 = 15</i>
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</pre>
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@@ -5960,12 +5961,13 @@ declare i64 @llvm.atomic.load.add.i64.( i64* <ptr>, i64 <delta> )
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<h5>Syntax:</h5>
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<p>
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This is an overloaded intrinsic. You can use <tt>llvm.atomic.load.sub</tt> on
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any integer bit width. Not all targets support all bit widths however.</p>
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any integer bit width and for different address spaces. Not all targets
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support all bit widths however.</p>
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<pre>
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declare i8 @llvm.atomic.load.sub.i8.( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.load.sub.i16.( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.load.sub.i32.( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.load.sub.i64.( i64* <ptr>, i64 <delta> )
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declare i8 @llvm.atomic.load.sub.i8.p0i32( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.load.sub.i16.p0i32( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.load.sub.i32.p0i32( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.load.sub.i64.p0i32( i64* <ptr>, i64 <delta> )
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</pre>
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<h5>Overview:</h5>
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@@ -5992,11 +5994,11 @@ declare i64 @llvm.atomic.load.sub.i64.( i64* <ptr>, i64 <delta> )
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<pre>
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%ptr = malloc i32
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store i32 8, %ptr
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%result1 = call i32 @llvm.atomic.load.sub.i32( i32* %ptr, i32 4 )
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%result1 = call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %ptr, i32 4 )
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<i>; yields {i32}:result1 = 8</i>
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%result2 = call i32 @llvm.atomic.load.sub.i32( i32* %ptr, i32 2 )
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%result2 = call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %ptr, i32 2 )
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<i>; yields {i32}:result2 = 4</i>
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%result3 = call i32 @llvm.atomic.load.sub.i32( i32* %ptr, i32 5 )
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%result3 = call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %ptr, i32 5 )
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<i>; yields {i32}:result3 = 2</i>
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%memval1 = load i32* %ptr <i>; yields {i32}:memval1 = -3</i>
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</pre>
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@@ -6015,37 +6017,37 @@ declare i64 @llvm.atomic.load.sub.i64.( i64* <ptr>, i64 <delta> )
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<p>
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These are overloaded intrinsics. You can use <tt>llvm.atomic.load_and</tt>,
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<tt>llvm.atomic.load_nand</tt>, <tt>llvm.atomic.load_or</tt>, and
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<tt>llvm.atomic.load_xor</tt> on any integer bit width. Not all targets
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support all bit widths however.</p>
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<tt>llvm.atomic.load_xor</tt> on any integer bit width and for different
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address spaces. Not all targets support all bit widths however.</p>
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<pre>
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declare i8 @llvm.atomic.load.and.i8.( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.load.and.i16.( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.load.and.i32.( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.load.and.i64.( i64* <ptr>, i64 <delta> )
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declare i8 @llvm.atomic.load.and.i8.p0i8( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.load.and.i16.p0i16( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.load.and.i32.p0i32( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.load.and.i64.p0i64( i64* <ptr>, i64 <delta> )
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</pre>
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<pre>
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declare i8 @llvm.atomic.load.or.i8.( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.load.or.i16.( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.load.or.i32.( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.load.or.i64.( i64* <ptr>, i64 <delta> )
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declare i8 @llvm.atomic.load.or.i8.p0i8( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.load.or.i16.p0i16( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.load.or.i32.p0i32( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.load.or.i64.p0i64( i64* <ptr>, i64 <delta> )
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</pre>
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<pre>
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declare i8 @llvm.atomic.load.nand.i8.( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.load.nand.i16.( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.load.nand.i32.( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.load.nand.i64.( i64* <ptr>, i64 <delta> )
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declare i8 @llvm.atomic.load.nand.i8.p0i32( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.load.nand.i16.p0i32( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.load.nand.i32.p0i32( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.load.nand.i64.p0i32( i64* <ptr>, i64 <delta> )
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</pre>
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<pre>
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declare i8 @llvm.atomic.load.xor.i8.( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.load.xor.i16.( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.load.xor.i32.( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.load.xor.i64.( i64* <ptr>, i64 <delta> )
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declare i8 @llvm.atomic.load.xor.i8.p0i32( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.load.xor.i16.p0i32( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.load.xor.i32.p0i32( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.load.xor.i64.p0i32( i64* <ptr>, i64 <delta> )
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</pre>
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<h5>Overview:</h5>
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@@ -6074,13 +6076,13 @@ declare i64 @llvm.atomic.load.xor.i64.( i64* <ptr>, i64 <delta> )
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<pre>
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%ptr = malloc i32
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store i32 0x0F0F, %ptr
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%result0 = call i32 @llvm.atomic.load.nand.i32( i32* %ptr, i32 0xFF )
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%result0 = call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %ptr, i32 0xFF )
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<i>; yields {i32}:result0 = 0x0F0F</i>
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%result1 = call i32 @llvm.atomic.load.and.i32( i32* %ptr, i32 0xFF )
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%result1 = call i32 @llvm.atomic.load.and.i32.p0i32( i32* %ptr, i32 0xFF )
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<i>; yields {i32}:result1 = 0xFFFFFFF0</i>
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%result2 = call i32 @llvm.atomic.load.or.i32( i32* %ptr, i32 0F )
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%result2 = call i32 @llvm.atomic.load.or.i32.p0i32( i32* %ptr, i32 0F )
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<i>; yields {i32}:result2 = 0xF0</i>
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%result3 = call i32 @llvm.atomic.load.xor.i32( i32* %ptr, i32 0F )
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%result3 = call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %ptr, i32 0F )
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<i>; yields {i32}:result3 = FF</i>
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%memval1 = load i32* %ptr <i>; yields {i32}:memval1 = F0</i>
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</pre>
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@@ -6100,37 +6102,38 @@ declare i64 @llvm.atomic.load.xor.i64.( i64* <ptr>, i64 <delta> )
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<p>
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These are overloaded intrinsics. You can use <tt>llvm.atomic.load_max</tt>,
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<tt>llvm.atomic.load_min</tt>, <tt>llvm.atomic.load_umax</tt>, and
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<tt>llvm.atomic.load_umin</tt> on any integer bit width. Not all targets
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<tt>llvm.atomic.load_umin</tt> on any integer bit width and for different
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address spaces. Not all targets
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support all bit widths however.</p>
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<pre>
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declare i8 @llvm.atomic.load.max.i8.( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.load.max.i16.( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.load.max.i32.( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.load.max.i64.( i64* <ptr>, i64 <delta> )
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declare i8 @llvm.atomic.load.max.i8.p0i8( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.load.max.i16.p0i16( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.load.max.i32.p0i32( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.load.max.i64.p0i64( i64* <ptr>, i64 <delta> )
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</pre>
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<pre>
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declare i8 @llvm.atomic.load.min.i8.( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.load.min.i16.( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.load.min.i32.( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.load.min.i64.( i64* <ptr>, i64 <delta> )
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declare i8 @llvm.atomic.load.min.i8.p0i8( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.load.min.i16.p0i16( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.load.min.i32..p0i32( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.load.min.i64..p0i64( i64* <ptr>, i64 <delta> )
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</pre>
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<pre>
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declare i8 @llvm.atomic.load.umax.i8.( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.load.umax.i16.( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.load.umax.i32.( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.load.umax.i64.( i64* <ptr>, i64 <delta> )
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declare i8 @llvm.atomic.load.umax.i8.p0i8( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.load.umax.i16.p0i16( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.load.umax.i32.p0i32( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.load.umax.i64.p0i64( i64* <ptr>, i64 <delta> )
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</pre>
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<pre>
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declare i8 @llvm.atomic.load.umin.i8.( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.load.umin.i16.( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.load.umin.i32.( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.load.umin.i64.( i64* <ptr>, i64 <delta> )
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declare i8 @llvm.atomic.load.umin.i8..p0i8( i8* <ptr>, i8 <delta> )
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declare i16 @llvm.atomic.load.umin.i16.p0i16( i16* <ptr>, i16 <delta> )
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declare i32 @llvm.atomic.load.umin.i32..p0i32( i32* <ptr>, i32 <delta> )
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declare i64 @llvm.atomic.load.umin.i64..p0i64( i64* <ptr>, i64 <delta> )
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</pre>
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<h5>Overview:</h5>
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@@ -6159,13 +6162,13 @@ declare i64 @llvm.atomic.load.umin.i64.( i64* <ptr>, i64 <delta> )
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<pre>
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%ptr = malloc i32
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store i32 7, %ptr
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%result0 = call i32 @llvm.atomic.load.min.i32( i32* %ptr, i32 -2 )
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%result0 = call i32 @llvm.atomic.load.min.i32.p0i32( i32* %ptr, i32 -2 )
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<i>; yields {i32}:result0 = 7</i>
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%result1 = call i32 @llvm.atomic.load.max.i32( i32* %ptr, i32 8 )
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%result1 = call i32 @llvm.atomic.load.max.i32.p0i32( i32* %ptr, i32 8 )
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<i>; yields {i32}:result1 = -2</i>
|
||||
%result2 = call i32 @llvm.atomic.load.umin.i32( i32* %ptr, i32 10 )
|
||||
%result2 = call i32 @llvm.atomic.load.umin.i32.p0i32( i32* %ptr, i32 10 )
|
||||
<i>; yields {i32}:result2 = 8</i>
|
||||
%result3 = call i32 @llvm.atomic.load.umax.i32( i32* %ptr, i32 30 )
|
||||
%result3 = call i32 @llvm.atomic.load.umax.i32.p0i32( i32* %ptr, i32 30 )
|
||||
<i>; yields {i32}:result3 = 8</i>
|
||||
%memval1 = load i32* %ptr <i>; yields {i32}:memval1 = 30</i>
|
||||
</pre>
|
||||
|
||||
Reference in New Issue
Block a user