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[Hexagon] Adding transfers to and from control registers.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224599 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2014-12-19 19:06:32 +00:00
parent 786e40311e
commit e403ffc801
3 changed files with 70 additions and 1 deletions
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23
lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
View File

@ -49,6 +49,9 @@ public:
};
}
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder);
static const uint16_t IntRegDecoderTable[] = {
Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
@ -82,6 +85,26 @@ static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
return MCDisassembler::Success;
}
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/, const void *Decoder) {
static const uint16_t CtrlRegDecoderTable[] = {
Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1,
Hexagon::P3_0, Hexagon::NoRegister, Hexagon::C6, Hexagon::C7,
Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP,
Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPCH
};
if (RegNo >= sizeof(CtrlRegDecoderTable) / sizeof(CtrlRegDecoderTable[0]))
return MCDisassembler::Fail;
if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister)
return MCDisassembler::Fail;
unsigned Register = CtrlRegDecoderTable[RegNo];
Inst.addOperand(MCOperand::CreateReg(Register));
return MCDisassembler::Success;
}
static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/, const void *Decoder) {
static const uint16_t DoubleRegDecoderTable[] = {

42
lib/Target/Hexagon/HexagonInstrInfo.td
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@ -3368,6 +3368,48 @@ defm J2_ploop2s : SPLOOP_ri<"2", 0b10>;
defm J2_ploop3s : SPLOOP_ri<"3", 0b11>;
}
// Transfer to/from Control/GPR Guest/GPR
let hasSideEffects = 0 in
class TFR_CR_RS_base<RegisterClass CTRC, RegisterClass RC, bit isDouble>
: CRInst <(outs CTRC:$dst), (ins RC:$src),
"$dst = $src", [], "", CR_tc_3x_SLOT3> {
bits<5> dst;
bits<5> src;
let IClass = 0b0110;
let Inst{27-25} = 0b001;
let Inst{24} = isDouble;
let Inst{23-21} = 0b001;
let Inst{20-16} = src;
let Inst{4-0} = dst;
}
let isCodeGenOnly = 0 in
def A2_tfrrcr : TFR_CR_RS_base<CtrRegs, IntRegs, 0b0>;
def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>;
def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>;
let hasSideEffects = 0 in
class TFR_RD_CR_base<RegisterClass RC, RegisterClass CTRC, bit isSingle>
: CRInst <(outs RC:$dst), (ins CTRC:$src),
"$dst = $src", [], "", CR_tc_3x_SLOT3> {
bits<5> dst;
bits<5> src;
let IClass = 0b0110;
let Inst{27-26} = 0b10;
let Inst{25} = isSingle;
let Inst{24-21} = 0b0000;
let Inst{20-16} = src;
let Inst{4-0} = dst;
}
let hasNewValue = 1, opNewValue = 0, isCodeGenOnly = 0 in
def A2_tfrcrr : TFR_RD_CR_base<IntRegs, CtrRegs, 1>;
def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>;
def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>;
// TFRI64 - assembly mapped.
let isReMaterializable = 1 in
def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),

6
test/MC/Disassembler/Hexagon/cr.txt
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@ -35,4 +35,8 @@
0x01 0xc0 0xc2 0x6b
# CHECK: p1 = not(p2)
0x01 0xc2 0x43 0x6b
# CHECK: p1 = xor(p3, p2)
# CHECK: p1 = xor(p3, p2)
0x0d 0xc0 0x35 0x62
# CHECK: cs1 = r21
0x11 0xc0 0x0d 0x6a
# CHECK: r17 = cs1