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Fixed the order of GPR RegisterClass regs to be: ..., R10, R11, R12, ...

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94455 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2010-01-25 21:56:35 +00:00
parent 26793ed974
commit e43b6c9695
1 changed files with 1 additions and 1 deletions
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2
lib/Target/ARM/ARMRegisterInfo.td
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@ -123,7 +123,7 @@ def FPSCR : ARMReg<1, "fpscr">;
// r10 == Stack Limit
//
def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
R7, R8, R9, R10, R12, R11,
R7, R8, R9, R10, R11, R12,
LR, SP, PC]> {
let MethodProtos = [{
iterator allocation_order_begin(const MachineFunction &MF) const;