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Simply ARM so_reg MIOperandInfo definitions.
The shift immediate encoding, printing, etc. is handled directly by the enclosing operand definition, so it should be a vanilla immediate, not a nested complex operand (shift_imm). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135968 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -411,7 +411,7 @@ def so_reg_reg : Operand<i32>, // reg reg imm
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let EncoderMethod = "getSORegRegOpValue";
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let PrintMethod = "printSORegRegOperand";
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let ParserMatchClass = ShiftedRegAsmOperand;
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let MIOperandInfo = (ops GPR, GPR, shift_imm);
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let MIOperandInfo = (ops GPR, GPR, i32imm);
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}
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def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
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@ -421,7 +421,7 @@ def so_reg_imm : Operand<i32>, // reg imm
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let EncoderMethod = "getSORegImmOpValue";
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let PrintMethod = "printSORegImmOperand";
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let ParserMatchClass = ShiftedImmAsmOperand;
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let MIOperandInfo = (ops GPR, shift_imm);
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let MIOperandInfo = (ops GPR, i32imm);
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}
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// FIXME: Does this need to be distinct from so_reg?
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@ -430,7 +430,7 @@ def shift_so_reg_reg : Operand<i32>, // reg reg imm
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[shl,srl,sra,rotr]> {
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let EncoderMethod = "getSORegRegOpValue";
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let PrintMethod = "printSORegRegOperand";
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let MIOperandInfo = (ops GPR, GPR, shift_imm);
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let MIOperandInfo = (ops GPR, GPR, i32imm);
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}
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// FIXME: Does this need to be distinct from so_reg?
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@ -439,7 +439,7 @@ def shift_so_reg_imm : Operand<i32>, // reg reg imm
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[shl,srl,sra,rotr]> {
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let EncoderMethod = "getSORegImmOpValue";
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let PrintMethod = "printSORegImmOperand";
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let MIOperandInfo = (ops GPR, shift_imm);
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let MIOperandInfo = (ops GPR, i32imm);
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}
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