mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-03 13:31:05 +00:00
The result of getSetCCResultType (eg: i32) may be larger
than the type an i1 is promoted to (eg: i8). Account for this. Noticed by Tilmann Scheller on CellSPU; he will hopefully take care of fixing this in LegalizeDAG and adding a testcase! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56997 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
a2582da44d
commit
e47561ccff
@ -365,10 +365,14 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
|
||||
}
|
||||
|
||||
SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
|
||||
assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0)))
|
||||
&& "SetCC type is not legal??");
|
||||
return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)),
|
||||
N->getOperand(0), N->getOperand(1), N->getOperand(2));
|
||||
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
|
||||
MVT SVT = TLI.getSetCCResultType(N->getOperand(0));
|
||||
assert(isTypeLegal(SVT) && "SetCC type not legal??");
|
||||
assert(NVT.getSizeInBits() <= SVT.getSizeInBits() &&
|
||||
"Integer type overpromoted?");
|
||||
return DAG.getNode(ISD::TRUNCATE, NVT,
|
||||
DAG.getNode(ISD::SETCC, SVT, N->getOperand(0),
|
||||
N->getOperand(1), N->getOperand(2)));
|
||||
}
|
||||
|
||||
SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
|
||||
|
Loading…
Reference in New Issue
Block a user