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[mips][mips64r6] Add LWPC and LWUPC instructions

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Differential Revision: http://reviews.llvm.org/D3788


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208971 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic 2014-05-16 10:27:10 +00:00
parent 5f32c76db1
commit e4dfc196e4
4 changed files with 15 additions and 4 deletions
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2
lib/Target/Mips/Mips32r6InstrFormats.td
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@ -35,6 +35,8 @@ class OPCODE2<bits<2> Val> {
bits<2> Value = Val;
}
def OPCODE2_ADDIUPC : OPCODE2<0b00>;
def OPCODE2_LWPC : OPCODE2<0b01>;
def OPCODE2_LWUPC : OPCODE2<0b10>;
class OPCODE5<bits<5> Val> {
bits<5> Value = Val;

13
lib/Target/Mips/Mips32r6InstrInfo.td
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@ -81,6 +81,9 @@ class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
@ -172,14 +175,16 @@ multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
//
//===----------------------------------------------------------------------===//
class ADDIUPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
class PCREL19_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
dag OutOperandList = (outs GPROpnd:$rs);
dag InOperandList = (ins simm19_lsl2:$imm);
string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
list<dag> Pattern = [];
}
class ADDIUPC_DESC : ADDIUPC_DESC_BASE<"addiupc", GPR32Opnd>;
class ADDIUPC_DESC : PCREL19_DESC_BASE<"addiupc", GPR32Opnd>;
class LWPC_DESC: PCREL19_DESC_BASE<"lwpc", GPR32Opnd>;
class LWUPC_DESC: PCREL19_DESC_BASE<"lwupc", GPR32Opnd>;
class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
Operand ImmOpnd> {
@ -347,8 +352,8 @@ def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
def JIALC;
def JIC;
// def LSA; // See MSA
def LWPC;
def LWUPC;
def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;

2
test/MC/Mips/mips32r6/valid.s
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@ -44,6 +44,8 @@
cmp.ngt.d $f2,$f3,$f4 # CHECK: cmp.ngt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f]
div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a]
divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b]
lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43]
lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43]
mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda]
modu $2,$3,$4 # CHECK: modu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdb]
# mul $2,$3,$4 # CHECK-TODO: mul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x98]

2
test/MC/Mips/mips64r6/valid.s
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@ -55,6 +55,8 @@
ddivu $2,$3,$4 # CHECK: ddivu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9f]
dmod $2,$3,$4 # CHECK: dmod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xde]
dmodu $2,$3,$4 # CHECK: dmodu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdf]
lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43]
lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43]
# mul $2,$3,$4 # CHECK-TODO: mul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x98]
muh $2,$3,$4 # CHECK: muh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd8]
mulu $2,$3,$4 # CHECK: mulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x99]