mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-27 13:30:05 +00:00
[Hexagon] Adding add/sub with carry, logical shift left by immediate and memop instructions. Removing old defs without bits and updating references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225210 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
1b84bf2554
commit
e4f1dcdb83
@ -1128,28 +1128,28 @@ isValidOffset(const int Opcode, const int Offset) const {
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return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
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(Offset <= Hexagon_ADDI_OFFSET_MAX);
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case Hexagon::MemOPw_ADDi_V4 :
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case Hexagon::MemOPw_SUBi_V4 :
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case Hexagon::MemOPw_ADDr_V4 :
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case Hexagon::MemOPw_SUBr_V4 :
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case Hexagon::MemOPw_ANDr_V4 :
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case Hexagon::MemOPw_ORr_V4 :
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case Hexagon::L4_iadd_memopw_io:
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case Hexagon::L4_isub_memopw_io:
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case Hexagon::L4_add_memopw_io:
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case Hexagon::L4_sub_memopw_io:
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case Hexagon::L4_and_memopw_io:
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case Hexagon::L4_or_memopw_io:
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return (0 <= Offset && Offset <= 255);
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case Hexagon::MemOPh_ADDi_V4 :
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case Hexagon::MemOPh_SUBi_V4 :
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case Hexagon::MemOPh_ADDr_V4 :
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case Hexagon::MemOPh_SUBr_V4 :
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case Hexagon::MemOPh_ANDr_V4 :
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case Hexagon::MemOPh_ORr_V4 :
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case Hexagon::L4_iadd_memoph_io:
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case Hexagon::L4_isub_memoph_io:
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case Hexagon::L4_add_memoph_io:
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case Hexagon::L4_sub_memoph_io:
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case Hexagon::L4_and_memoph_io:
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case Hexagon::L4_or_memoph_io:
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return (0 <= Offset && Offset <= 127);
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case Hexagon::MemOPb_ADDi_V4 :
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case Hexagon::MemOPb_SUBi_V4 :
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case Hexagon::MemOPb_ADDr_V4 :
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case Hexagon::MemOPb_SUBr_V4 :
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case Hexagon::MemOPb_ANDr_V4 :
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case Hexagon::MemOPb_ORr_V4 :
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case Hexagon::L4_iadd_memopb_io:
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case Hexagon::L4_isub_memopb_io:
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case Hexagon::L4_add_memopb_io:
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case Hexagon::L4_sub_memopb_io:
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case Hexagon::L4_and_memopb_io:
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case Hexagon::L4_or_memopb_io:
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return (0 <= Offset && Offset <= 63);
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// LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
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@ -1206,31 +1206,31 @@ isMemOp(const MachineInstr *MI) const {
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switch (MI->getOpcode())
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{
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default: return false;
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case Hexagon::MemOPw_ADDi_V4 :
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case Hexagon::MemOPw_SUBi_V4 :
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case Hexagon::MemOPw_ADDr_V4 :
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case Hexagon::MemOPw_SUBr_V4 :
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case Hexagon::MemOPw_ANDr_V4 :
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case Hexagon::MemOPw_ORr_V4 :
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case Hexagon::MemOPh_ADDi_V4 :
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case Hexagon::MemOPh_SUBi_V4 :
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case Hexagon::MemOPh_ADDr_V4 :
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case Hexagon::MemOPh_SUBr_V4 :
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case Hexagon::MemOPh_ANDr_V4 :
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case Hexagon::MemOPh_ORr_V4 :
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case Hexagon::MemOPb_ADDi_V4 :
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case Hexagon::MemOPb_SUBi_V4 :
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case Hexagon::MemOPb_ADDr_V4 :
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case Hexagon::MemOPb_SUBr_V4 :
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case Hexagon::MemOPb_ANDr_V4 :
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case Hexagon::MemOPb_ORr_V4 :
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case Hexagon::MemOPb_SETBITi_V4:
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case Hexagon::MemOPh_SETBITi_V4:
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case Hexagon::MemOPw_SETBITi_V4:
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case Hexagon::MemOPb_CLRBITi_V4:
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case Hexagon::MemOPh_CLRBITi_V4:
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case Hexagon::MemOPw_CLRBITi_V4:
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default: return false;
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case Hexagon::L4_iadd_memopw_io:
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case Hexagon::L4_isub_memopw_io:
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case Hexagon::L4_add_memopw_io:
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case Hexagon::L4_sub_memopw_io:
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case Hexagon::L4_and_memopw_io:
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case Hexagon::L4_or_memopw_io:
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case Hexagon::L4_iadd_memoph_io:
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case Hexagon::L4_isub_memoph_io:
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case Hexagon::L4_add_memoph_io:
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case Hexagon::L4_sub_memoph_io:
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case Hexagon::L4_and_memoph_io:
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case Hexagon::L4_or_memoph_io:
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case Hexagon::L4_iadd_memopb_io:
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case Hexagon::L4_isub_memopb_io:
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case Hexagon::L4_add_memopb_io:
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case Hexagon::L4_sub_memopb_io:
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case Hexagon::L4_and_memopb_io:
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case Hexagon::L4_or_memopb_io:
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case Hexagon::L4_ior_memopb_io:
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case Hexagon::L4_ior_memoph_io:
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case Hexagon::L4_ior_memopw_io:
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case Hexagon::L4_iand_memopb_io:
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case Hexagon::L4_iand_memoph_io:
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case Hexagon::L4_iand_memopw_io:
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return true;
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}
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return false;
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@ -2239,158 +2239,54 @@ let hasNewValue = 1, Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23,
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isCodeGenOnly = 0 in
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def A4_round_rr_sat : T_S3op_3 < "round", IntRegs, 0b11, 0b11, 1>;
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// Shift by immediate and accumulate.
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// Rx=add(#u8,asl(Rx,#U5))
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let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
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validSubTargets = HasV4SubT in
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def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
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(ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
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"$dst = add(#$src1, asl($src2, #$src3))",
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[(set (i32 IntRegs:$dst),
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(add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
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u8ExtPred:$src1))],
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"$src2 = $dst">,
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Requires<[HasV4T]>;
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// Rdd=[add|sub](Rss,Rtt,Px):carry
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let isPredicateLate = 1, hasSideEffects = 0 in
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class T_S3op_carry <string mnemonic, bits<3> MajOp>
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: SInst < (outs DoubleRegs:$Rdd, PredRegs:$Px),
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(ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
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"$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu):carry",
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[], "$Px = $Pu", S_3op_tc_1_SLOT23 > {
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bits<5> Rdd;
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bits<5> Rss;
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bits<5> Rtt;
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bits<2> Pu;
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// Rx=add(#u8,lsr(Rx,#U5))
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let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
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validSubTargets = HasV4SubT in
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def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
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(ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
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"$dst = add(#$src1, lsr($src2, #$src3))",
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[(set (i32 IntRegs:$dst),
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(add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
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u8ExtPred:$src1))],
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"$src2 = $dst">,
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Requires<[HasV4T]>;
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let IClass = 0b1100;
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// Rx=sub(#u8,asl(Rx,#U5))
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let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
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validSubTargets = HasV4SubT in
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def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
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(ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
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"$dst = sub(#$src1, asl($src2, #$src3))",
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[(set (i32 IntRegs:$dst),
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(sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
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u8ExtPred:$src1))],
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"$src2 = $dst">,
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Requires<[HasV4T]>;
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let Inst{27-24} = 0b0010;
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let Inst{23-21} = MajOp;
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let Inst{20-16} = Rss;
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let Inst{12-8} = Rtt;
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let Inst{6-5} = Pu;
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let Inst{4-0} = Rdd;
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}
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// Rx=sub(#u8,lsr(Rx,#U5))
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let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
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validSubTargets = HasV4SubT in
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def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
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(ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
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"$dst = sub(#$src1, lsr($src2, #$src3))",
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[(set (i32 IntRegs:$dst),
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(sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
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u8ExtPred:$src1))],
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"$src2 = $dst">,
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Requires<[HasV4T]>;
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//Shift by immediate and logical.
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//Rx=and(#u8,asl(Rx,#U5))
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let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
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validSubTargets = HasV4SubT in
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def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
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(ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
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"$dst = and(#$src1, asl($src2, #$src3))",
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[(set (i32 IntRegs:$dst),
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(and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
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u8ExtPred:$src1))],
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"$src2 = $dst">,
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Requires<[HasV4T]>;
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//Rx=and(#u8,lsr(Rx,#U5))
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let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
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validSubTargets = HasV4SubT in
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def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
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(ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
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"$dst = and(#$src1, lsr($src2, #$src3))",
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[(set (i32 IntRegs:$dst),
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(and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
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u8ExtPred:$src1))],
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"$src2 = $dst">,
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Requires<[HasV4T]>;
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//Rx=or(#u8,asl(Rx,#U5))
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let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
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AddedComplexity = 30, validSubTargets = HasV4SubT in
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def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
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(ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
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"$dst = or(#$src1, asl($src2, #$src3))",
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[(set (i32 IntRegs:$dst),
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(or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
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u8ExtPred:$src1))],
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"$src2 = $dst">,
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Requires<[HasV4T]>;
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//Rx=or(#u8,lsr(Rx,#U5))
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let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
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AddedComplexity = 30, validSubTargets = HasV4SubT in
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def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
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(ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
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"$dst = or(#$src1, lsr($src2, #$src3))",
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[(set (i32 IntRegs:$dst),
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(or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
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u8ExtPred:$src1))],
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"$src2 = $dst">,
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Requires<[HasV4T]>;
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//Shift by register.
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//Rd=lsl(#s6,Rt)
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let validSubTargets = HasV4SubT in {
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def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),
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"$dst = lsl(#$src1, $src2)",
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[(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1,
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(i32 IntRegs:$src2)))]>,
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Requires<[HasV4T]>;
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//Shift by register and logical.
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//Rxx^=asl(Rss,Rt)
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def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
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(ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
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"$dst ^= asl($src2, $src3)",
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[(set (i64 DoubleRegs:$dst),
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(xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2),
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(i32 IntRegs:$src3))))],
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"$src1 = $dst">,
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Requires<[HasV4T]>;
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//Rxx^=asr(Rss,Rt)
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def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
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(ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
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"$dst ^= asr($src2, $src3)",
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[(set (i64 DoubleRegs:$dst),
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(xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2),
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(i32 IntRegs:$src3))))],
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"$src1 = $dst">,
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Requires<[HasV4T]>;
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//Rxx^=lsl(Rss,Rt)
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def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
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(ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
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"$dst ^= lsl($src2, $src3)",
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[(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
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(shl (i64 DoubleRegs:$src2),
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(i32 IntRegs:$src3))))],
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"$src1 = $dst">,
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Requires<[HasV4T]>;
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//Rxx^=lsr(Rss,Rt)
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def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
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(ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
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"$dst ^= lsr($src2, $src3)",
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[(set (i64 DoubleRegs:$dst),
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(xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2),
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(i32 IntRegs:$src3))))],
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"$src1 = $dst">,
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Requires<[HasV4T]>;
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let isCodeGenOnly = 0 in {
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def A4_addp_c : T_S3op_carry < "add", 0b110 >;
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def A4_subp_c : T_S3op_carry < "sub", 0b111 >;
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}
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// Shift an immediate left by register amount.
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let hasNewValue = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
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def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6Imm:$s6, IntRegs:$Rt),
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"$Rd = lsl(#$s6, $Rt)" ,
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[(set (i32 IntRegs:$Rd), (shl s6ImmPred:$s6,
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(i32 IntRegs:$Rt)))],
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"", S_3op_tc_1_SLOT23> {
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bits<5> Rd;
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bits<6> s6;
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bits<5> Rt;
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let IClass = 0b1100;
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let Inst{27-22} = 0b011010;
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let Inst{20-16} = s6{5-1};
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let Inst{12-8} = Rt;
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let Inst{7-6} = 0b11;
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let Inst{4-0} = Rd;
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let Inst{5} = s6{0};
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}
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//===----------------------------------------------------------------------===//
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// XTYPE/SHIFT -
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//===----------------------------------------------------------------------===//
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@ -2478,7 +2374,7 @@ class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
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(ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
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opc#"($base+#$offset)"#memOp#"$delta",
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[]>,
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Requires<[HasV4T, UseMEMOP]> {
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Requires<[UseMEMOP]> {
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bits<5> base;
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bits<5> delta;
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@ -2489,6 +2385,7 @@ class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
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!if (!eq(opcBits, 0b01), offset{6-1},
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!if (!eq(opcBits, 0b10), offset{7-2},0)));
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let opExtentAlign = opcBits;
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let IClass = 0b0011;
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let Inst{27-24} = 0b1110;
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let Inst{22-21} = opcBits;
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@ -2509,7 +2406,7 @@ class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
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opc#"($base+#$offset)"#memOp#"#$delta"
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#!if(memOpBits{1},")", ""), // clrbit, setbit - include ')'
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[]>,
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Requires<[HasV4T, UseMEMOP]> {
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Requires<[UseMEMOP]> {
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bits<5> base;
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bits<5> delta;
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@ -2520,6 +2417,7 @@ class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
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!if (!eq(opcBits, 0b01), offset{6-1},
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!if (!eq(opcBits, 0b10), offset{7-2},0)));
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let opExtentAlign = opcBits;
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let IClass = 0b0011;
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let Inst{27-24} = 0b1111;
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let Inst{22-21} = opcBits;
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@ -2532,36 +2430,36 @@ class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
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// multiclass to define MemOp instructions with register operand.
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multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
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def _ADD#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
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def _SUB#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
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def _AND#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
|
||||
def _OR#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
|
||||
def L4_add#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
|
||||
def L4_sub#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
|
||||
def L4_and#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
|
||||
def L4_or#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
|
||||
}
|
||||
|
||||
// multiclass to define MemOp instructions with immediate Operand.
|
||||
multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
|
||||
def _ADD#NAME#_V4 : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
|
||||
def _SUB#NAME#_V4 : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
|
||||
def _CLRBIT#NAME#_V4 : MemOp_ri_base<opc, opcBits, ImmOp, " =clrbit(", 0b10>;
|
||||
def _SETBIT#NAME#_V4 : MemOp_ri_base<opc, opcBits, ImmOp, " =setbit(", 0b11>;
|
||||
def L4_iadd#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
|
||||
def L4_isub#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
|
||||
def L4_iand#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = clrbit(", 0b10>;
|
||||
def L4_ior#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = setbit(", 0b11>;
|
||||
}
|
||||
|
||||
multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
|
||||
defm r : MemOp_rr <opc, opcBits, ImmOp>;
|
||||
defm i : MemOp_ri <opc, opcBits, ImmOp>;
|
||||
defm _#NAME : MemOp_rr <opc, opcBits, ImmOp>;
|
||||
defm _#NAME : MemOp_ri <opc, opcBits, ImmOp>;
|
||||
}
|
||||
|
||||
// Define MemOp instructions.
|
||||
let isExtendable = 1, opExtendable = 1, isExtentSigned = 0,
|
||||
validSubTargets =HasV4SubT in {
|
||||
let opExtentBits = 6, accessSize = ByteAccess in
|
||||
defm MemOPb : MemOp_base <"memb", 0b00, u6_0Ext>;
|
||||
validSubTargets =HasV4SubT in {
|
||||
let opExtentBits = 6, accessSize = ByteAccess, isCodeGenOnly = 0 in
|
||||
defm memopb_io : MemOp_base <"memb", 0b00, u6_0Ext>;
|
||||
|
||||
let opExtentBits = 7, accessSize = HalfWordAccess in
|
||||
defm MemOPh : MemOp_base <"memh", 0b01, u6_1Ext>;
|
||||
let opExtentBits = 7, accessSize = HalfWordAccess, isCodeGenOnly = 0 in
|
||||
defm memoph_io : MemOp_base <"memh", 0b01, u6_1Ext>;
|
||||
|
||||
let opExtentBits = 8, accessSize = WordAccess in
|
||||
defm MemOPw : MemOp_base <"memw", 0b10, u6_2Ext>;
|
||||
let opExtentBits = 8, accessSize = WordAccess, isCodeGenOnly = 0 in
|
||||
defm memopw_io : MemOp_base <"memw", 0b10, u6_2Ext>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -2594,10 +2492,10 @@ multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
|
||||
multiclass MemOpi_u5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
|
||||
// Half Word
|
||||
defm : MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
|
||||
MemOPh_ADDi_V4, MemOPh_SUBi_V4>;
|
||||
L4_iadd_memoph_io, L4_isub_memoph_io>;
|
||||
// Byte
|
||||
defm : MemOpi_u5ALUOp <ldOpByte, truncstorei8, u6ExtPred,
|
||||
MemOPb_ADDi_V4, MemOPb_SUBi_V4>;
|
||||
L4_iadd_memopb_io, L4_isub_memopb_io>;
|
||||
}
|
||||
|
||||
let Predicates = [HasV4T, UseMEMOP] in {
|
||||
@ -2606,8 +2504,8 @@ let Predicates = [HasV4T, UseMEMOP] in {
|
||||
defm : MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
|
||||
|
||||
// Word
|
||||
defm : MemOpi_u5ALUOp <load, store, u6_2ExtPred, MemOPw_ADDi_V4,
|
||||
MemOPw_SUBi_V4>;
|
||||
defm : MemOpi_u5ALUOp <load, store, u6_2ExtPred, L4_iadd_memopw_io,
|
||||
L4_isub_memopw_io>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -2635,10 +2533,10 @@ multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
|
||||
multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
|
||||
// Half Word
|
||||
defm : MemOpi_m5Pats <ldOpHalf, truncstorei16, u6_1ExtPred, m5HImmPred,
|
||||
ADDRriU6_1, MEMOPIMM_HALF, MemOPh_SUBi_V4>;
|
||||
ADDRriU6_1, MEMOPIMM_HALF, L4_isub_memoph_io>;
|
||||
// Byte
|
||||
defm : MemOpi_m5Pats <ldOpByte, truncstorei8, u6ExtPred, m5BImmPred,
|
||||
ADDRriU6_0, MEMOPIMM_BYTE, MemOPb_SUBi_V4>;
|
||||
ADDRriU6_0, MEMOPIMM_BYTE, L4_isub_memopb_io>;
|
||||
}
|
||||
|
||||
let Predicates = [HasV4T, UseMEMOP] in {
|
||||
@ -2648,7 +2546,7 @@ let Predicates = [HasV4T, UseMEMOP] in {
|
||||
|
||||
// Word
|
||||
defm : MemOpi_m5Pats <load, store, u6_2ExtPred, m5ImmPred,
|
||||
ADDRriU6_2, MEMOPIMM, MemOPw_SUBi_V4>;
|
||||
ADDRriU6_2, MEMOPIMM, L4_isub_memopw_io>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -2679,16 +2577,16 @@ multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
|
||||
multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
|
||||
// Byte - clrbit
|
||||
defm : MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u6ExtPred,
|
||||
ADDRriU6_0, CLRMEMIMM_BYTE, MemOPb_CLRBITi_V4, and>;
|
||||
ADDRriU6_0, CLRMEMIMM_BYTE, L4_iand_memopb_io, and>;
|
||||
// Byte - setbit
|
||||
defm : MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u6ExtPred,
|
||||
ADDRriU6_0, SETMEMIMM_BYTE, MemOPb_SETBITi_V4, or>;
|
||||
ADDRriU6_0, SETMEMIMM_BYTE, L4_ior_memopb_io, or>;
|
||||
// Half Word - clrbit
|
||||
defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u6_1ExtPred,
|
||||
ADDRriU6_1, CLRMEMIMM_SHORT, MemOPh_CLRBITi_V4, and>;
|
||||
ADDRriU6_1, CLRMEMIMM_SHORT, L4_iand_memoph_io, and>;
|
||||
// Half Word - setbit
|
||||
defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u6_1ExtPred,
|
||||
ADDRriU6_1, SETMEMIMM_SHORT, MemOPh_SETBITi_V4, or>;
|
||||
ADDRriU6_1, SETMEMIMM_SHORT, L4_ior_memoph_io, or>;
|
||||
}
|
||||
|
||||
let Predicates = [HasV4T, UseMEMOP] in {
|
||||
@ -2701,9 +2599,9 @@ let Predicates = [HasV4T, UseMEMOP] in {
|
||||
// memw(Rs+#0) = [clrbit|setbit](#U5)
|
||||
// memw(Rs+#u6:2) = [clrbit|setbit](#U5)
|
||||
defm : MemOpi_bitPats<load, store, Clr5ImmPred, u6_2ExtPred, ADDRriU6_2,
|
||||
CLRMEMIMM, MemOPw_CLRBITi_V4, and>;
|
||||
CLRMEMIMM, L4_iand_memopw_io, and>;
|
||||
defm : MemOpi_bitPats<load, store, Set5ImmPred, u6_2ExtPred, ADDRriU6_2,
|
||||
SETMEMIMM, MemOPw_SETBITi_V4, or>;
|
||||
SETMEMIMM, L4_ior_memopw_io, or>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -2744,12 +2642,12 @@ multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp,
|
||||
multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
|
||||
// Half Word
|
||||
defm : MemOPr_ALUOp <ldOpHalf, truncstorei16, ADDRriU6_1, u6_1ExtPred,
|
||||
MemOPh_ADDr_V4, MemOPh_SUBr_V4,
|
||||
MemOPh_ANDr_V4, MemOPh_ORr_V4>;
|
||||
L4_add_memoph_io, L4_sub_memoph_io,
|
||||
L4_and_memoph_io, L4_or_memoph_io>;
|
||||
// Byte
|
||||
defm : MemOPr_ALUOp <ldOpByte, truncstorei8, ADDRriU6_0, u6ExtPred,
|
||||
MemOPb_ADDr_V4, MemOPb_SUBr_V4,
|
||||
MemOPb_ANDr_V4, MemOPb_ORr_V4>;
|
||||
L4_add_memopb_io, L4_sub_memopb_io,
|
||||
L4_and_memopb_io, L4_or_memopb_io>;
|
||||
}
|
||||
|
||||
// Define 'def Pats' for MemOps with register addend.
|
||||
@ -2759,8 +2657,8 @@ let Predicates = [HasV4T, UseMEMOP] in {
|
||||
defm : MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
|
||||
defm : MemOPr_ExtType<extloadi8, extloadi16>; // any extend
|
||||
// Word
|
||||
defm : MemOPr_ALUOp <load, store, ADDRriU6_2, u6_2ExtPred, MemOPw_ADDr_V4,
|
||||
MemOPw_SUBr_V4, MemOPw_ANDr_V4, MemOPw_ORr_V4 >;
|
||||
defm : MemOPr_ALUOp <load, store, ADDRriU6_2, u6_2ExtPred, L4_add_memopw_io,
|
||||
L4_sub_memopw_io, L4_and_memopw_io, L4_or_memopw_io >;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
50
test/MC/Disassembler/Hexagon/memop.txt
Normal file
50
test/MC/Disassembler/Hexagon/memop.txt
Normal file
@ -0,0 +1,50 @@
|
||||
# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
|
||||
|
||||
0x95 0xd9 0x11 0x3e
|
||||
# CHECK: memb(r17+#51) += r21
|
||||
0xb5 0xd9 0x11 0x3e
|
||||
# CHECK: memb(r17+#51) -= r21
|
||||
0xd5 0xd9 0x11 0x3e
|
||||
# CHECK: memb(r17+#51) &= r21
|
||||
0xf5 0xd9 0x11 0x3e
|
||||
# CHECK: memb(r17+#51) |= r21
|
||||
0x95 0xd9 0x11 0x3f
|
||||
# CHECK: memb(r17+#51) += #21
|
||||
0xb5 0xd9 0x11 0x3f
|
||||
# CHECK: memb(r17+#51) -= #21
|
||||
0xd5 0xd9 0x11 0x3f
|
||||
# CHECK: memb(r17+#51) = clrbit(#21)
|
||||
0xf5 0xd9 0x11 0x3f
|
||||
# CHECK: memb(r17+#51) = setbit(#21)
|
||||
0x95 0xd9 0x31 0x3e
|
||||
# CHECK: memh(r17+#102) += r21
|
||||
0xb5 0xd9 0x31 0x3e
|
||||
# CHECK: memh(r17+#102) -= r21
|
||||
0xd5 0xd9 0x31 0x3e
|
||||
# CHECK: memh(r17+#102) &= r21
|
||||
0xf5 0xd9 0x31 0x3e
|
||||
# CHECK: memh(r17+#102) |= r21
|
||||
0x95 0xd9 0x31 0x3f
|
||||
# CHECK: memh(r17+#102) += #21
|
||||
0xb5 0xd9 0x31 0x3f
|
||||
# CHECK: memh(r17+#102) -= #21
|
||||
0xd5 0xd9 0x31 0x3f
|
||||
# CHECK: memh(r17+#102) = clrbit(#21)
|
||||
0xf5 0xd9 0x31 0x3f
|
||||
# CHECK: memh(r17+#102) = setbit(#21)
|
||||
0x95 0xd9 0x51 0x3e
|
||||
# CHECK: memw(r17+#204) += r21
|
||||
0xb5 0xd9 0x51 0x3e
|
||||
# CHECK: memw(r17+#204) -= r21
|
||||
0xd5 0xd9 0x51 0x3e
|
||||
# CHECK: memw(r17+#204) &= r21
|
||||
0xf5 0xd9 0x51 0x3e
|
||||
# CHECK: memw(r17+#204) |= r21
|
||||
0x95 0xd9 0x51 0x3f
|
||||
# CHECK: memw(r17+#204) += #21
|
||||
0xb5 0xd9 0x51 0x3f
|
||||
# CHECK: memw(r17+#204) -= #21
|
||||
0xd5 0xd9 0x51 0x3f
|
||||
# CHECK: memw(r17+#204) = clrbit(#21)
|
||||
0xf5 0xd9 0x51 0x3f
|
||||
# CHECK: memw(r17+#204) = setbit(#21)
|
||||
@ -44,6 +44,10 @@
|
||||
# CHECK: r17 = add(r21.h, r31.l):sat:<<16
|
||||
0xf1 0xd5 0x5f 0xd5
|
||||
# CHECK: r17 = add(r21.h, r31.h):sat:<<16
|
||||
0x70 0xde 0xd4 0xc2
|
||||
# CHECK: r17:16 = add(r21:20, r31:30, p3):carry
|
||||
0x70 0xde 0xf4 0xc2
|
||||
# CHECK: r17:16 = sub(r21:20, r31:30, p3):carry
|
||||
0x90 0xc0 0x94 0x80
|
||||
# CHECK: r17:16 = not(r21:20)
|
||||
0xf0 0xde 0x14 0xd3
|
||||
|
||||
@ -106,6 +106,8 @@
|
||||
# CHECK: r17 = asl(r21, r31)
|
||||
0xd1 0xdf 0x55 0xc6
|
||||
# CHECK: r17 = lsl(r21, r31)
|
||||
0xf1 0xdf 0x8a 0xc6
|
||||
# CHECK: r17 = lsl(#21, r31)
|
||||
0x10 0xdf 0x94 0xcb
|
||||
# CHECK: r17:16 -= asr(r21:20, r31)
|
||||
0x50 0xdf 0x94 0xcb
|
||||
|
||||
Loading…
Reference in New Issue
Block a user