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VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.

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Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138163 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2011-08-20 00:17:25 +00:00
parent 4cc2328e4e
commit e5038e191d
3 changed files with 33 additions and 59 deletions
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41
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -628,7 +628,7 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
bool SPRDest = ARM::SPRRegClass.contains(DestReg);
bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
unsigned Opc;
unsigned Opc = 0;
if (SPRDest && SPRSrc) {
Opc = ARM::VMOVS;
@ -668,17 +668,38 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
Opc = ARM::VORRq;
else if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
Opc = ARM::VMOVQQ;
else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
Opc = ARM::VMOVQQQQ;
else
llvm_unreachable("Impossible reg-to-reg copy");
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
MIB.addReg(SrcReg, getKillRegState(KillSrc));
if (Opc == ARM::VORRq)
if (Opc) {
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
MIB.addReg(SrcReg, getKillRegState(KillSrc));
if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
AddDefaultPred(MIB);
if (Opc == ARM::VORRq)
MIB.addReg(SrcReg, getKillRegState(KillSrc));
if (Opc != ARM::VMOVQQ)
AddDefaultPred(MIB);
return;
}
// Expand the MOVQQQQ pseudo instruction in place.
if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
const TargetRegisterInfo *TRI = &getRegisterInfo();
assert(ARM::qsub_0 + 3 == ARM::qsub_3 && "Expected contiguous enum.");
for (unsigned i = ARM::qsub_0, e = ARM::qsub_3 + 1; i != e; ++i) {
unsigned Dst = TRI->getSubReg(DestReg, i);
unsigned Src = TRI->getSubReg(SrcReg, i);
MachineInstrBuilder Mov =
AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VORRq))
.addReg(Dst, RegState::Define)
.addReg(Src, getKillRegState(KillSrc))
.addReg(Src, getKillRegState(KillSrc)));
if (i == ARM::qsub_3) {
Mov->addRegisterDefined(DestReg, TRI);
if (KillSrc)
Mov->addRegisterKilled(SrcReg, TRI);
}
}
return;
}
llvm_unreachable("Impossible reg-to-reg copy");
}
static const

46
lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -998,52 +998,6 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
return true;
}
case ARM::VMOVQQQQ: {
unsigned DstReg = MI.getOperand(0).getReg();
bool DstIsDead = MI.getOperand(0).isDead();
unsigned Dst0 = TRI->getSubReg(DstReg, ARM::qsub_0);
unsigned Dst1 = TRI->getSubReg(DstReg, ARM::qsub_1);
unsigned Dst2 = TRI->getSubReg(DstReg, ARM::qsub_2);
unsigned Dst3 = TRI->getSubReg(DstReg, ARM::qsub_3);
unsigned SrcReg = MI.getOperand(1).getReg();
bool SrcIsKill = MI.getOperand(1).isKill();
unsigned Src0 = TRI->getSubReg(SrcReg, ARM::qsub_0);
unsigned Src1 = TRI->getSubReg(SrcReg, ARM::qsub_1);
unsigned Src2 = TRI->getSubReg(SrcReg, ARM::qsub_2);
unsigned Src3 = TRI->getSubReg(SrcReg, ARM::qsub_3);
MachineInstrBuilder Mov0 =
AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(ARM::VORRq))
.addReg(Dst0,
RegState::Define | getDeadRegState(DstIsDead))
.addReg(Src0, getKillRegState(SrcIsKill))
.addReg(Src0, getKillRegState(SrcIsKill)));
MachineInstrBuilder Mov1 =
AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(ARM::VORRq))
.addReg(Dst1,
RegState::Define | getDeadRegState(DstIsDead))
.addReg(Src1, getKillRegState(SrcIsKill))
.addReg(Src1, getKillRegState(SrcIsKill)));
MachineInstrBuilder Mov2 =
AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(ARM::VORRq))
.addReg(Dst2,
RegState::Define | getDeadRegState(DstIsDead))
.addReg(Src2, getKillRegState(SrcIsKill))
.addReg(Src2, getKillRegState(SrcIsKill)));
MachineInstrBuilder Mov3 =
AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(ARM::VORRq))
.addReg(Dst3,
RegState::Define | getDeadRegState(DstIsDead))
.addReg(Src3, getKillRegState(SrcIsKill))
.addReg(Src3, getKillRegState(SrcIsKill)));
TransferImpOps(MI, Mov0, Mov3);
MI.eraseFromParent();
return true;
}
case ARM::VLDMQIA: {
unsigned NewOpc = ARM::VLDMDIA;
MachineInstrBuilder MIB =

5
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll
View File

@ -1,7 +1,6 @@
; RUN: llc %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 -O0 -o -
; The following test is supposed to produce a VMOVQQQQ pseudo instruction.
; Make sure that it gets expanded; otherwise, the compile fails when trying
; to print the pseudo-instruction.
; Make sure that the VMOVQQQQ pseudo instruction is handled properly
; by codegen.
define void @test_vmovqqqq_pseudo() nounwind ssp {
entry: