6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-04-04 10:30:01 +00:00
Code Issues Projects Releases Wiki Activity

Move some methods out of MachineInstr into MachineOperand

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28102 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-05-04 17:52:23 +00:00
parent e3158308e0
commit e53f4a055f
15 changed files with 56 additions and 70 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
include/llvm/CodeGen/MachineInstr.h
View File

@ -234,7 +234,7 @@ public:
extra.regNum = Reg;
}
void setImmedValue(int immVal) {
void setImmedValue(int64_t immVal) {
assert(isImmediate() && "Wrong MachineOperand mutator");
contents.immedVal = immVal;
}
@ -245,6 +245,22 @@ public:
"Wrong MachineOperand accessor");
extra.offset = Offset;
}
/// ChangeToImmediate - Replace this operand with a new immediate operand of
/// the specified value. If an operand is known to be an immediate already,
/// the setImmedValue method should be used.
void ChangeToImmediate(int64_t ImmVal) {
opType = MO_Immediate;
contents.immedVal = ImmVal;
}
/// ChangeToRegister - Replace this operand with a new register operand of
/// the specified value. If an operand is known to be an register already,
/// the setReg method should be used.
void ChangeToRegister(unsigned Reg) {
opType = MO_VirtualRegister;
extra.regNum = Reg;
}
friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
@ -436,7 +452,6 @@ public:
//===--------------------------------------------------------------------===//
// Accessors used to modify instructions in place.
//
// FIXME: Move this stuff to MachineOperand itself!
/// setOpcode - Replace the opcode of the current instruction with a new one.
///
@ -448,14 +463,6 @@ public:
void RemoveOperand(unsigned i) {
operands.erase(operands.begin()+i);
}
// Access to set the operands when building the machine instruction
//
void SetMachineOperandConst(unsigned i,
MachineOperand::MachineOperandType operandType,
int intValue);
void SetMachineOperandReg(unsigned i, int regNum);
};
//===----------------------------------------------------------------------===//

6
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -187,7 +187,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
MRegisterInfo::isVirtualRegister(mop.getReg())) {
// replace register with representative register
unsigned reg = rep(mop.getReg());
mii->SetMachineOperandReg(i, reg);
mii->getOperand(i).setReg(reg);
LiveInterval &RegInt = getInterval(reg);
RegInt.weight +=
@ -263,7 +263,7 @@ addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
if (NewRegLiveIn && mop.isUse()) {
// We already emitted a reload of this value, reuse it for
// subsequent operands.
MI->SetMachineOperandReg(i, NewRegLiveIn);
MI->getOperand(i).setReg(NewRegLiveIn);
DEBUG(std::cerr << "\t\t\t\treused reload into reg" << NewRegLiveIn
<< " for operand #" << i << '\n');
} else if (MachineInstr* fmi = mri_->foldMemoryOperand(MI, i, slot)) {
@ -300,7 +300,7 @@ addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
// create a new register for this spill
NewRegLiveIn = mf_->getSSARegMap()->createVirtualRegister(rc);
MI->SetMachineOperandReg(i, NewRegLiveIn);
MI->getOperand(i).setReg(NewRegLiveIn);
vrm.grow();
vrm.assignVirt2StackSlot(NewRegLiveIn, slot);
LiveInterval& nI = getOrCreateInterval(NewRegLiveIn);

19
lib/CodeGen/MachineInstr.cpp
View File

@ -107,25 +107,6 @@ bool MachineInstr::OperandsComplete() const {
return false;
}
void
MachineInstr::SetMachineOperandConst(unsigned i,
MachineOperand::MachineOperandType opTy,
int intValue) {
assert(i < getNumOperands());
operands[i].opType = opTy;
operands[i].contents.immedVal = intValue;
operands[i].extra.regNum = -1;
operands[i].flags = 0;
}
void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
assert(i < getNumOperands());
operands[i].opType = MachineOperand::MO_VirtualRegister;
operands[i].contents.GV = NULL;
operands[i].extra.regNum = regNum;
}
void MachineInstr::dump() const {
std::cerr << " " << *this;
}

6
lib/CodeGen/RegAllocLocal.cpp
View File

@ -443,7 +443,7 @@ MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
// and return.
if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
MarkPhysRegRecentlyUsed(PR); // Already have this value available!
MI->SetMachineOperandReg(OpNum, PR); // Assign the input register
MI->getOperand(OpNum).setReg(PR); // Assign the input register
return MI;
}
@ -481,7 +481,7 @@ MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
++NumLoads; // Update statistics
PhysRegsEverUsed[PhysReg] = true;
MI->SetMachineOperandReg(OpNum, PhysReg); // Assign the input register
MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
return MI;
}
@ -599,7 +599,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
DestPhysReg = getReg(MBB, MI, DestVirtReg);
PhysRegsEverUsed[DestPhysReg] = true;
markVirtRegModified(DestVirtReg);
MI->SetMachineOperandReg(i, DestPhysReg); // Assign the output register
MI->getOperand(i).setReg(DestPhysReg); // Assign the output register
}
}

2
lib/CodeGen/RegAllocSimple.cpp
View File

@ -211,7 +211,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
Virt2PhysRegMap[virtualReg] = physReg;
}
}
MI->SetMachineOperandReg(i, physReg);
MI->getOperand(i).setReg(physReg);
DEBUG(std::cerr << "virt: " << virtualReg <<
", phys: " << op.getReg() << "\n");
}

2
lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@ -200,7 +200,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
if (mi->getOperand(i).isRegister() &&
mi->getOperand(i).getReg() == regB)
mi->SetMachineOperandReg(i, regA);
mi->getOperand(i).setReg(regA);
}
}

16
lib/CodeGen/VirtRegMap.cpp
View File

@ -182,7 +182,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
}
}
PhysRegsUsed[PhysReg] = true;
MI.SetMachineOperandReg(i, PhysReg);
MI.getOperand(i).setReg(PhysReg);
} else {
PhysRegsUsed[MO.getReg()] = true;
}
@ -458,7 +458,7 @@ namespace {
// Any stores to this stack slot are not dead anymore.
MaybeDeadStores.erase(NewOp.StackSlot);
MI->SetMachineOperandReg(NewOp.Operand, NewPhysReg);
MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Spills.addAvailable(NewOp.StackSlot, NewPhysReg);
++NumLoads;
@ -536,7 +536,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
// This virtual register was assigned a physreg!
unsigned Phys = VRM.getPhys(VirtReg);
PhysRegsUsed[Phys] = true;
MI.SetMachineOperandReg(i, Phys);
MI.getOperand(i).setReg(Phys);
continue;
}
@ -567,7 +567,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
<< MRI->getName(PhysReg) << " for vreg"
<< VirtReg <<" instead of reloading into physreg "
<< MRI->getName(VRM.getPhys(VirtReg)) << "\n");
MI.SetMachineOperandReg(i, PhysReg);
MI.getOperand(i).setReg(PhysReg);
// The only technical detail we have is that we don't know that
// PhysReg won't be clobbered by a reloaded stack slot that occurs
@ -618,7 +618,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
<< MRI->getName(PhysReg) << " for vreg"
<< VirtReg
<< " instead of reloading into same physreg.\n");
MI.SetMachineOperandReg(i, PhysReg);
MI.getOperand(i).setReg(PhysReg);
++NumReused;
continue;
}
@ -633,7 +633,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
Spills.ClobberPhysReg(DesignatedReg);
Spills.addAvailable(StackSlot, DesignatedReg);
MI.SetMachineOperandReg(i, DesignatedReg);
MI.getOperand(i).setReg(DesignatedReg);
DEBUG(std::cerr << '\t' << *prior(MII));
++NumReused;
continue;
@ -662,7 +662,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
MaybeDeadStores.erase(StackSlot);
Spills.addAvailable(StackSlot, PhysReg);
++NumLoads;
MI.SetMachineOperandReg(i, PhysReg);
MI.getOperand(i).setReg(PhysReg);
DEBUG(std::cerr << '\t' << *prior(MII));
}
@ -817,7 +817,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
PhysRegsUsed[PhysReg] = true;
MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
DEBUG(std::cerr << "Store:\t" << *next(MII));
MI.SetMachineOperandReg(i, PhysReg);
MI.getOperand(i).setReg(PhysReg);
// Check to see if this is a noop copy. If so, eliminate the
// instruction before considering the dest reg to be changed.

9
lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -216,7 +216,7 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
int FrameIndex = MI.getOperand(i).getFrameIndex();
// Add the base register of R30 (SP) or R15 (FP).
MI.SetMachineOperandReg(i + 1, FP ? Alpha::R15 : Alpha::R30);
MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30);
// Now add the frame object offset to the offset from the virtual frame index.
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
@ -233,15 +233,14 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
//so in this case, we need to use a temporary register, and move the original
//inst off the SP/FP
//fix up the old:
MI.SetMachineOperandReg(i + 1, Alpha::R28);
MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate,
getLower16(Offset));
MI.getOperand(i + 1).ChangeToRegister(Alpha::R28);
MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
//insert the new
MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28)
.addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
MBB.insert(II, nMI);
} else {
MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate, Offset);
MI.getOperand(i).ChangeToImmediate(Offset);
}
}

6
lib/Target/IA64/IA64RegisterInfo.cpp
View File

@ -155,7 +155,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const
// choose a base register: ( hasFP? framepointer : stack pointer )
unsigned BaseRegister = FP ? IA64::r5 : IA64::r12;
// Add the base register
MI.SetMachineOperandReg(i, BaseRegister);
MI.getOperand(i).ChangeToRegister(BaseRegister);
// Now add the frame object offset to the offset from r1.
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
@ -168,7 +168,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const
// XXX: we use 'r22' as another hack+slash temporary register here :(
if ( Offset <= 8191 && Offset >= -8192) { // smallish offset
//fix up the old:
MI.SetMachineOperandReg(i, IA64::r22);
MI.getOperand(i).ChangeToRegister(IA64::r22);
MI.getOperand(i).setUse(); // mark r22 as being used
// (the bundler wants to know this)
//insert the new
@ -177,7 +177,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const
MBB.insert(II, nMI);
} else { // it's big
//fix up the old:
MI.SetMachineOperandReg(i, IA64::r22);
MI.getOperand(i).ChangeToRegister(IA64::r22);
MI.getOperand(i).setUse(); // mark r22 as being used
// (the bundler wants to know this)
MachineInstr* nMI;

4
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -136,8 +136,8 @@ MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
// Swap op1/op2
unsigned Reg1 = MI->getOperand(1).getReg();
unsigned Reg2 = MI->getOperand(2).getReg();
MI->SetMachineOperandReg(2, Reg1);
MI->SetMachineOperandReg(1, Reg2);
MI->getOperand(2).setReg(Reg1);
MI->getOperand(1).setReg(Reg2);
// Swap the mask around.
unsigned MB = MI->getOperand(4).getImmedValue();

8
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -294,7 +294,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
int FrameIndex = MI.getOperand(i).getFrameIndex();
// Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1);
// Take into account whether it's an add or mem instruction
unsigned OffIdx = (i == 2) ? 1 : 2;
@ -321,8 +321,8 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
"No indexed form of load or store available!");
unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
MI.setOpcode(NewOpcode);
MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
MI.SetMachineOperandReg(2, PPC::R0);
MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg());
MI.getOperand(2).ChangeToRegister(PPC::R0);
} else {
switch (MI.getOpcode()) {
case PPC::LWA:
@ -333,7 +333,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
Offset >>= 2; // The actual encoded value has the low two bits zero.
break;
}
MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_Immediate, Offset);
MI.getOperand(OffIdx).ChangeToImmediate(Offset);
}
}

4
lib/Target/Sparc/FPMover.cpp
View File

@ -104,8 +104,8 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
else
assert(0 && "Unknown opcode!");
MI->SetMachineOperandReg(0, EvenDestReg);
MI->SetMachineOperandReg(1, EvenSrcReg);
MI->getOperand(0).setReg(EvenDestReg);
MI->getOperand(1).setReg(EvenSrcReg);
DEBUG(std::cerr << "FPMover: the modified instr is: " << *MI);
// Insert copy for the other half of the double.
if (DestDReg != SrcDReg) {

9
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -135,8 +135,8 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
if (Offset >= -4096 && Offset <= 4095) {
// If the offset is small enough to fit in the immediate field, directly
// encode it.
MI.SetMachineOperandReg(i, SP::I6);
MI.SetMachineOperandConst(i+1, MachineOperand::MO_Immediate, Offset);
MI.getOperand(i).ChangeToRegister(SP::I6);
MI.getOperand(i+1).ChangeToImmediate(Offset);
} else {
// Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
// scavenge a register here instead of reserving G1 all of the time.
@ -146,9 +146,8 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
BuildMI(*MI.getParent(), II, SP::ADDrr, 2,
SP::G1).addReg(SP::G1).addReg(SP::I6);
// Insert: G1+%lo(offset) into the user.
MI.SetMachineOperandReg(i, SP::G1);
MI.SetMachineOperandConst(i+1, MachineOperand::MO_Immediate,
Offset & ((1 << 10)-1));
MI.getOperand(i).ChangeToRegister(SP::G1);
MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
}
}

4
lib/Target/TargetInstrInfo.cpp
View File

@ -46,7 +46,7 @@ MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const {
"This only knows how to commute register operands so far");
unsigned Reg1 = MI->getOperand(1).getReg();
unsigned Reg2 = MI->getOperand(1).getReg();
MI->SetMachineOperandReg(2, Reg1);
MI->SetMachineOperandReg(1, Reg2);
MI->getOperand(2).setReg(Reg1);
MI->getOperand(1).setReg(Reg2);
return MI;
}

4
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -665,7 +665,7 @@ void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
// This must be part of a four operand memory reference. Replace the
// FrameIndex with base register with EBP. Add add an offset to the offset.
MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP);
MI.getOperand(i).ChangeToRegister(hasFP(MF) ? X86::EBP : X86::ESP);
// Now add the frame object offset to the offset from EBP.
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
@ -676,7 +676,7 @@ void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
else
Offset += 4; // Skip the saved EBP
MI.SetMachineOperandConst(i+3, MachineOperand::MO_Immediate, Offset);
MI.getOperand(i+3).ChangeToImmediate(Offset);
}
void